Alternatives and similar repositories for NPU_X_Interface

Users that are interested in NPU_X_Interface are comparing it to the libraries listed below

• kuladeepsaireddy / OpenNoc
  ☆40Updated 6 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆40Updated 3 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆61Updated 3 years ago
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆14Updated 3 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆44Updated 3 years ago
• gju06051 / TPU_HW_Verilog
  ☆14Updated 2 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆42Updated 3 years ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆159Updated 10 months ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆28Updated 6 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆60Updated 3 weeks ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆30Updated 6 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆55Updated 4 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆18Updated 4 years ago
• Nikola2444 / RISC-V-vector-processor
  ☆15Updated 3 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆17Updated last year
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆21Updated 4 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆33Updated 5 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆79Updated 7 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆80Updated 11 years ago
• wubinyi / Convolutional-Neural-Network-Accelerator
  Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).
  ☆20Updated 7 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆67Updated 3 years ago
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆77Updated last month
• mfkiwl / E203_dma
  ☆11Updated 5 years ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆23Updated 9 months ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆32Updated last year
• canbozaci / Cache
  L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
  ☆15Updated 3 years ago