gururaj-s / streamlineView external linksLinks
Streamline Covert Channel Attack (presented in ASPLOS'21)
☆22Feb 18, 2021Updated 4 years ago
Alternatives and similar repositories for streamline
Users that are interested in streamline are comparing it to the libraries listed below
Sorting:
- MIRAGE (USENIX Security 2021)☆14Nov 8, 2023Updated 2 years ago
- ☆17Jun 26, 2025Updated 7 months ago
- The open-source component of Prime+Scope, published at CCS 2021☆37Jul 18, 2023Updated 2 years ago
- Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…☆53Jun 25, 2019Updated 6 years ago
- HW interface for memory caches☆28Apr 21, 2020Updated 5 years ago
- GitHub (mirror) repository for the Mastik toolkit, written by Yuval Yarom https://cs.adelaide.edu.au/~yval/Mastik/☆42Sep 19, 2019Updated 6 years ago
- ☆21Jun 17, 2022Updated 3 years ago
- ☆13May 26, 2022Updated 3 years ago
- Automated test generator to detectcache side channel leakages.☆11Jul 1, 2019Updated 6 years ago
- ☆13Jun 22, 2019Updated 6 years ago
- New Cache implementation using Gem5☆13Apr 2, 2014Updated 11 years ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆62Aug 7, 2022Updated 3 years ago
- Tool for testing and finding minimal eviction sets☆107May 6, 2021Updated 4 years ago
- NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems [USENIX Security '23]☆19Nov 17, 2022Updated 3 years ago
- Reload+Refresh PoC☆16Feb 26, 2020Updated 5 years ago
- Repository of the paper "Reproducing Spectre Attack with gem5, How To Do It Right?"☆18Jul 27, 2023Updated 2 years ago
- ☆20Aug 3, 2018Updated 7 years ago
- This upload contains the artifacts for the paper "SLAP: Data Speculation Attacks via Load Address Prediction on Apple Silicon", to appear…☆22Jan 26, 2025Updated last year
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆61Apr 27, 2020Updated 5 years ago
- ☆30Feb 20, 2024Updated last year
- Slice-aware Memory Management - Exploiting NUCA Characteristic of LLC in Intel Processors☆41May 20, 2019Updated 6 years ago
- Defeating Pointer Authentication on the Apple M1 with Hardware Attacks☆48Aug 12, 2022Updated 3 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Mar 29, 2021Updated 4 years ago
- (elastic) cuckoo hashing☆15Jun 20, 2020Updated 5 years ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆18Feb 3, 2026Updated last week
- Code to evaluate XLATE attacks as well existing cache attacks.☆31Aug 17, 2018Updated 7 years ago
- ☆48Dec 19, 2018Updated 7 years ago
- ☆119Nov 14, 2022Updated 3 years ago
- The artifact for SecSMT paper -- Usenix Security 2022☆31Oct 4, 2022Updated 3 years ago
- Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)☆34Mar 28, 2025Updated 10 months ago
- This repository contains some tools to monitor the UNC_CBO_CACHE_LOOKUP event of the C-Boxes.☆12Oct 11, 2017Updated 8 years ago
- ☆15Dec 15, 2022Updated 3 years ago
- Code for the CCS 2022 paper "Microarchitectural Leakage Templates and Their Application to Cache-Based Side Channels".☆17Oct 17, 2022Updated 3 years ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆57Aug 21, 2019Updated 6 years ago
- A flush-reload side channel attack implementation☆56Mar 26, 2022Updated 3 years ago
- PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software FIESTA - Fault Injection Evaluation with Statistic…☆41Updated this week
- ☆16Mar 18, 2025Updated 10 months ago
- Proof-of-concept implementation for the paper "SegScope: Probing Fine-grained Interrupts via Architectural Footprints" (HPCA'24)☆19Jan 26, 2026Updated 3 weeks ago
- ☆17Aug 25, 2022Updated 3 years ago