Alternatives and similar repositories for cachequery

Users that are interested in cachequery are comparing it to the libraries listed below

• cgvwzq / polca
  Tool for inferring cache replacement policies with automata learning. Uses LearnLib and Sketch.
  ☆16Updated 5 years ago
• vusec / tlbdr
  ☆18Updated 2 years ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆20Updated 4 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆25Updated 9 months ago
• zzrcxb / LLCFeasible
  Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)
  ☆25Updated 2 months ago
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆61Updated 2 years ago
• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆21Updated 4 years ago
• renxida / iseedeaduops-poc
  Proof-of-concept for I See Dead Micro-Ops transient execution attack
  ☆14Updated 3 years ago
• cispa / Microarchitectural-Hash-Function-Recovery
  Proof-of-concept implementation for the paper "Efficient and Generic Microarchitectural Hash-Function Recovery" (IEEE S&P 2024)
  ☆30Updated last year
• KULeuven-COSIC / PRIME-SCOPE
  The open-source component of Prime+Scope, published at CCS 2021
  ☆32Updated last year
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆23Updated last year
• CPU-THU / Spectre-V4-ng
  The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…
  ☆21Updated last year
• greenlsi / reload_refresh
  Reload+Refresh PoC
  ☆15Updated 5 years ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 4 years ago
• FPSG-UIUC / Peek-a-Walk
  Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"
  ☆19Updated 3 months ago
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆60Updated 5 years ago
• flowyroll / uarchsec
  ☆45Updated 6 years ago
• vernamlab / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆20Updated 4 years ago
• nagnagnet / PrimeProbe
  ☆18Updated 6 years ago
• dskarlatos / MicroScope
  Microscope: Enabling Microarchitectural Replay Attacks
  ☆19Updated 4 years ago
• FPSG-UIUC / Pandora
  Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data
  ☆21Updated 2 years ago
• cispa / regcheck
  Proof-of-concept implementation for the paper "Reviving Meltdown 3a" (ESORICS 2023)
  ☆15Updated last year
• fanyao / branchspec
  Proof of concept code for the BranchSpec exploit.
  ☆9Updated 2 years ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆13Updated last year
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 4 months ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆21Updated 2 years ago
• isec-tugraz / halfdouble
  ☆16Updated 2 years ago
• PittECEArch / AdversarialPrefetch
  ☆19Updated 3 years ago