HW interface for memory caches
☆28Apr 21, 2020Updated 5 years ago
Alternatives and similar repositories for cachequery
Users that are interested in cachequery are comparing it to the libraries listed below
Sorting:
- Tool for inferring cache replacement policies with automata learning. Uses LearnLib and Sketch.☆16Apr 21, 2020Updated 5 years ago
- Tool for testing and finding minimal eviction sets☆106May 6, 2021Updated 4 years ago
- The open-source component of Prime+Scope, published at CCS 2021☆37Jul 18, 2023Updated 2 years ago
- reverse engineering branch predictors☆18Feb 28, 2016Updated 10 years ago
- ☆13May 26, 2022Updated 3 years ago
- The artifact for SecSMT paper -- Usenix Security 2022☆31Oct 4, 2022Updated 3 years ago
- ☆20Aug 3, 2018Updated 7 years ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆63Aug 7, 2022Updated 3 years ago
- ☆16Mar 18, 2025Updated last year
- ☆21Jun 17, 2022Updated 3 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆61Apr 27, 2020Updated 5 years ago
- ☆14Feb 18, 2021Updated 5 years ago
- MIRAGE (USENIX Security 2021)☆14Nov 8, 2023Updated 2 years ago
- Reload+Refresh PoC☆16Feb 26, 2020Updated 6 years ago
- ☆118Nov 14, 2022Updated 3 years ago
- XML representation of the x86 instruction set☆29Feb 15, 2026Updated last month
- This tool set can generate required capabilities for binaries. A system call to capability mapping is used to assign capability to the bi…☆14Oct 26, 2022Updated 3 years ago
- Performance Counter Measurements at the cycle granularity☆19Jul 9, 2021Updated 4 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆28Jun 25, 2025Updated 8 months ago
- This repository contains some tools to monitor the UNC_CBO_CACHE_LOOKUP event of the C-Boxes.☆12Oct 11, 2017Updated 8 years ago
- Code for the CCS 2022 paper "Microarchitectural Leakage Templates and Their Application to Cache-Based Side Channels".☆16Oct 17, 2022Updated 3 years ago
- A tool for running small microbenchmarks on recent Intel and AMD x86 CPUs.☆509Mar 7, 2026Updated 2 weeks ago
- Proof-of-concept code for the SMoTherSpectre exploit.☆77Nov 12, 2019Updated 6 years ago
- Proof-of-concept implementation for the paper "Efficient and Generic Microarchitectural Hash-Function Recovery" (IEEE S&P 2024)☆33Aug 30, 2023Updated 2 years ago
- ☆16Jul 28, 2022Updated 3 years ago
- ☆10Nov 14, 2022Updated 3 years ago
- A C implementation of AES got from OpenSSL☆14Dec 19, 2011Updated 14 years ago
- Reverse Engineering Page Table Caches in Your Processor☆374May 5, 2021Updated 4 years ago
- Automatic detection of speculative information flows☆75Jul 14, 2021Updated 4 years ago
- CacheDirector - Sending Packets to the Right Slice by Exploiting Intel Last-Level Cache Addressing☆12Apr 29, 2019Updated 6 years ago
- prime+probe code targeting a given physical address on libgcrypt run in an SGX enclave☆15Dec 6, 2018Updated 7 years ago
- Research Artifact for HPCA'24 Paper: *Modeling, Derivation, and Automated Analysis of Branch Predictor Security Vulnerabilities*.☆11Oct 30, 2025Updated 4 months ago
- Benchmark for memory store throughput☆23Jun 22, 2021Updated 4 years ago
- AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks☆46May 19, 2023Updated 2 years ago
- Trigger the rowhammer bug on ARMv8☆35Apr 14, 2019Updated 6 years ago
- ☆46Jul 19, 2023Updated 2 years ago
- [MICRO'20] LENS: A Low-level NVRAM Profiler [USENIX Security'23] NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems☆14Jul 8, 2024Updated last year
- ☆18Sep 4, 2023Updated 2 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated last year