pierreay / reproduce-spectre-gem5Links
Repository of the paper "Reproducing Spectre Attack with gem5, How To Do It Right?"
☆17Updated last year
Alternatives and similar repositories for reproduce-spectre-gem5
Users that are interested in reproduce-spectre-gem5 are comparing it to the libraries listed below
Sorting:
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆20Updated 4 years ago
- Reload+Refresh PoC☆14Updated 5 years ago
- Medusa Repository: Transynther tool and Medusa Attack☆20Updated 4 years ago
- The open-source component of Prime+Scope, published at CCS 2021☆31Updated last year
- The artifact for SecSMT paper -- Usenix Security 2022☆27Updated 2 years ago
- ☆18Updated 2 years ago
- Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…☆48Updated 5 years ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- Medusa Repository: Transynther tool and Medusa Attack☆21Updated 4 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- Proof of concept code for the BranchSpec exploit.☆9Updated 2 years ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆61Updated 2 years ago
- The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…☆21Updated last year
- Library for Prime+Probe cache side-channel attacks on L1 and L2☆34Updated 4 years ago
- ☆25Updated 2 years ago
- HW interface for memory caches☆28Updated 5 years ago
- Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.☆10Updated 5 years ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆52Updated 5 years ago
- Code to evaluate XLATE attacks as well existing cache attacks.☆31Updated 6 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆67Updated 2 months ago
- ☆38Updated last year
- ☆18Updated 6 years ago
- A flush-reload side channel attack implementation☆50Updated 3 years ago
- A tool for detecting Spectre vulnerabilities through fuzzing☆41Updated 3 years ago
- ☆12Updated 5 years ago
- ☆44Updated 6 years ago
- Tool for testing and finding minimal eviction sets☆103Updated 4 years ago
- ☆19Updated 2 years ago
- ☆16Updated 2 years ago
- Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)☆57Updated 3 years ago