0x161e-swei / covert-channel-101View external linksLinks
☆13Jun 22, 2019Updated 6 years ago
Alternatives and similar repositories for covert-channel-101
Users that are interested in covert-channel-101 are comparing it to the libraries listed below
Sorting:
- Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementatio…☆53Jun 25, 2019Updated 6 years ago
- ☆20Aug 3, 2018Updated 7 years ago
- Streamline Covert Channel Attack (presented in ASPLOS'21)☆22Feb 18, 2021Updated 4 years ago
- This repository contains some tools to monitor the UNC_CBO_CACHE_LOOKUP event of the C-Boxes.☆12Oct 11, 2017Updated 8 years ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆57Aug 21, 2019Updated 6 years ago
- MIRAGE (USENIX Security 2021)☆14Nov 8, 2023Updated 2 years ago
- CleanupSpec (MICRO-2019)☆16Oct 22, 2020Updated 5 years ago
- Reload+Refresh PoC☆16Feb 26, 2020Updated 5 years ago
- ☆22Jun 24, 2019Updated 6 years ago
- This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.☆24Jan 17, 2024Updated 2 years ago
- [arXiv'18] Security Analysis of Deep Neural Networks Operating in the Presence of Cache Side-Channel Attacks☆20Feb 19, 2020Updated 5 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆61Apr 27, 2020Updated 5 years ago
- A flush-reload side channel attack implementation☆56Mar 26, 2022Updated 3 years ago
- Tool for testing and finding minimal eviction sets☆107May 6, 2021Updated 4 years ago
- ☆119Nov 14, 2022Updated 3 years ago
- Pythia is a set of RDMA-based remote side-channel attacks. USENIX Security 2019.☆30Oct 24, 2020Updated 5 years ago
- [UNMAINTAINED] Implementation of the FLUSH+RELOAD side channel attack☆63Nov 4, 2017Updated 8 years ago
- Artifact, reproducibility, and testing utilites for gem5☆23Jul 1, 2021Updated 4 years ago
- PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software FIESTA - Fault Injection Evaluation with Statistic…☆41Updated this week
- ☆45Jul 19, 2023Updated 2 years ago
- Releasing open-sourced version of the code used in the paper "Perceptron-based Prefetch Filtering (ISCA 2019)"☆10May 27, 2022Updated 3 years ago
- GitHub (mirror) repository for the Mastik toolkit, written by Yuval Yarom https://cs.adelaide.edu.au/~yval/Mastik/☆42Sep 19, 2019Updated 6 years ago
- Library for Prime+Probe cache side-channel attacks on L1 and L2☆38Jun 10, 2020Updated 5 years ago
- This repository contains several tools to perform Cache Template Attacks☆164Nov 11, 2025Updated 3 months ago
- 一个旨在整理黑客常用工具的GitHub项目☆12Dec 13, 2023Updated 2 years ago
- Read physical page locations from arbitrary Linux programs☆13Jun 20, 2017Updated 8 years ago
- ☆12Sep 18, 2024Updated last year
- A gitbook named studying-containerd-notes☆10Dec 17, 2018Updated 7 years ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Mar 29, 2021Updated 4 years ago
- Efficient-Tensor-Management-on-HM-for-Deep-Learning☆10Nov 15, 2021Updated 4 years ago
- Example of Chisel3 Diplomacy☆11Feb 23, 2022Updated 3 years ago
- Source code for DABANGG attack.☆10Mar 26, 2022Updated 3 years ago
- This repository contains examples of Flush+Flush cache attacks☆169Oct 12, 2021Updated 4 years ago
- Container startup benchmark tool☆12Apr 10, 2023Updated 2 years ago
- All the verilog code I wrote in hardware Course☆10Sep 22, 2019Updated 6 years ago
- Instruction Pointer Classifier and Dynamic Degree Stream based Hardware Cache Prefetching☆16Nov 16, 2019Updated 6 years ago
- Source code of the U-TRR methodology presented in "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHamme…☆17Nov 15, 2022Updated 3 years ago
- ☆13May 26, 2022Updated 3 years ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆18Feb 3, 2026Updated 2 weeks ago