mstump / verilog-vga-controller
A very simple VGA controller written in verilog
☆24Updated 12 years ago
Alternatives and similar repositories for verilog-vga-controller:
Users that are interested in verilog-vga-controller are comparing it to the libraries listed below
- A RISC-V processor☆14Updated 6 years ago
- openMSP430 CPU core (from OpenCores)☆22Updated 2 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆63Updated 7 years ago
- A extremely size-optimized RV32I soft processor for FPGA.☆27Updated 6 years ago
- Atom Hardware IDE☆13Updated 4 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- ☆14Updated 7 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- SoftCPU/SoC engine-V☆54Updated last month
- 5-stage RISC-V CPU, originally developed for RISCBoy☆27Updated last year
- Wishbone interconnect utilities☆40Updated 2 months ago
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆16Updated 2 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆28Updated last year
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆82Updated 4 years ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆20Updated 4 years ago
- UART 16550 core☆34Updated 10 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- SDIO Device Verilog Core☆22Updated 6 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated last month
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- FPGA implementation of the 8051 Microcontroller (Verilog)☆48Updated 10 years ago
- Educational 16-bit MIPS Processor☆17Updated 6 years ago
- turbo 8051☆29Updated 7 years ago
- JTAG Test Access Port (TAP)☆33Updated 10 years ago
- Hardware design with Chisel☆32Updated 2 years ago
- The specification for the FIRRTL language☆54Updated this week
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated this week
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 9 months ago
- ☆31Updated last week