Alternatives and similar repositories for mips32r1_core

Users that are interested in mips32r1_core are comparing it to the libraries listed below

• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• bwitherspoon / rv32cpu
  A RISC-V processor
  ☆15Updated 6 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆85Updated 5 years ago
• grantae / mips32r1_xum
  A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old Uni…
  ☆60Updated 10 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆60Updated 4 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆123Updated 6 years ago
• riscv / riscv-test-env
  ☆49Updated 3 months ago
• rajshadow / 4-way-set-associative-cache-verilog
  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
  ☆41Updated 8 years ago
• google / bottlerocket
  ☆109Updated 6 years ago
• freecores / turbo8051
  turbo 8051
  ☆29Updated 7 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆102Updated 6 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 5 months ago
• maidenone / ORGFXSoC
  An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)
  ☆72Updated 13 years ago
• lajanugen / 8051
  FPGA implementation of the 8051 Microcontroller (Verilog)
  ☆49Updated 10 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆88Updated 4 years ago
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆74Updated 8 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆56Updated 4 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 10 months ago
• andrewandrepowell / zybo_petalinux_video_hls
  Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.
  ☆25Updated 8 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆90Updated 7 years ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆56Updated last year
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆58Updated 5 years ago