Alternatives and similar repositories for USB2I2S

Users that are interested in USB2I2S are comparing it to the libraries listed below

• ultraembedded / core_audio
  Audio controller (I2S, SPDIF, DAC)
  ☆88Updated 6 years ago
• briansune / Delta-Sigma-DAC-Verilog
  Delta Sigma DAC FPGA
  ☆43Updated 6 months ago
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆72Updated 3 years ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆118Updated 4 years ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆81Updated 4 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆72Updated 3 years ago
• Hello-FPGA / ZYNQ7020_Core_Board
  This is xc7z020clg400 FPGA hardware core board design
  ☆60Updated last year
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆40Updated 5 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆93Updated 5 years ago
• maxs-well / ad7606-driver-verilog
  AD7606 driver verilog
  ☆44Updated 6 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆87Updated 2 years ago
• kazkojima / pcm2pdm-example
  A tiny example of PCM to PDM pipeline on FPGA
  ☆22Updated 3 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆95Updated 5 years ago
• ApotheoTech / Aper-Oculus
  An open-source Xilinx Kria SOM Carrier for high-speed camera design
  ☆28Updated last year
• lvgl / lv_port_xilinx_zedboard_vitis
  This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals
  ☆27Updated last year
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆134Updated 2 years ago
• dawsonjon / FPGA-radio
  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
  ☆109Updated 8 years ago
• amaranth-farm / usb2-highspeed-core
  a USB2 highspeed device core, written in amaranth HDL
  ☆50Updated 11 months ago
• MatejGomboc / Verilog-I2S-Transciever
  I2S transciever implemented in Verilog HDL
  ☆31Updated 7 years ago
• gabriel-tenma-white / sdr5
  Design files for sdr5 prototype (Zynq + AD9363)
  ☆106Updated 5 years ago
• DiegoRosales / VHDL_Modules
  VHDL Modules
  ☆24Updated 10 years ago
• thinkoco / microsoft_fpga
  Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP
  ☆58Updated 2 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆60Updated 4 years ago
• pbing / FM_Radio
  Simple mono FM Radio.
  ☆48Updated 9 years ago
• circuitvalley / mipi_dsi_bridge_fpga
  Source code of MIPI DSI Bridge Published on https://www.circuitvalley.com
  ☆109Updated last year
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆72Updated last year
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆46Updated 4 years ago
• vanbwodonk / ft2232hl-jtag-clone
  Digilent JTAG clone hardware + eeprom firmware (.bin)
  ☆66Updated 3 years ago
• ChinaQMTECH / QMTECH_XC7K325T_CORE_BOARD
  ☆39Updated 3 years ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆96Updated 11 months ago