i2s core, with support for both transmit and receive
☆33May 24, 2018Updated 8 years ago
Alternatives and similar repositories for i2s
Users that are interested in i2s are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- I2S transciever implemented in Verilog HDL☆33Oct 11, 2017Updated 8 years ago
- Audio controller (I2S, SPDIF, DAC)☆101Sep 1, 2019Updated 7 years ago
- Synthesizable SystemVerilog IP-Core of the I2S Receiver☆11Jun 7, 2020Updated 6 years ago
- Open Hardware Zynq System on Module☆31Jul 25, 2015Updated 11 years ago
- A version of f32c/arduino that works with the SpinalHDL Vexriscv Murax SoC☆14May 23, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A simple (audio) synthesizer on the iCEBreaker FPGA.☆27Jan 26, 2020Updated 6 years ago
- Design and Verification of a Complete Application Specific Integrated Circuit☆12Nov 21, 2016Updated 9 years ago
- A Rust backend crate for the popular card game, Blackjack, designed to also be compiled for linking with C☆11Sep 17, 2019Updated 7 years ago
- 移植AD7606和AD9910的驱动，并且增加FFT运算☆14Aug 30, 2020Updated 6 years ago
- HDMI Expansion Modules compatible with the Pmod standard☆12Apr 5, 2018Updated 8 years ago
- ulx3s ghdl examples☆15Mar 6, 2021Updated 5 years ago
- Self-contained RTL to GDS flow for simple chip designs☆76Jul 7, 2026Updated 2 months ago
- USB HID host demo for STM32F4 Discovery : gcc + make☆12Jan 28, 2013Updated 13 years ago
- RaspberryPi print server for the HPGL plotter at the Brickyard Collaborative.☆11Mar 4, 2020Updated 6 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- use IR positioning camera to get transformation matrix between the object and camera☆12Jul 24, 2017Updated 9 years ago
- FPGA based MIDI keyboard project for EEE 304 (Digital Electronics Laboratory)☆14Sep 21, 2022Updated 3 years ago
- Files and libraries belonging to the getting started guide "Serial communication with the freeDSP"☆11Apr 14, 2016Updated 10 years ago
- A plugin to allow Jenkins Steps with Cadence vManager API☆10Jan 15, 2026Updated 8 months ago
- ☆10Dec 17, 2022Updated 3 years ago
- A small and flexible MPD client that may act as standalone application for an audio system.☆11Apr 17, 2023Updated 3 years ago
- Open Hardware carrier board supporting modules with Zynq 7000 All Programmable SoC devices.☆72Aug 7, 2023Updated 3 years ago
- S/PDIF receiver with support of compressed formats☆10Dec 8, 2024Updated last year
- Play a casual game of blackjack in the terminal. Written in Rust. 🂱🂫☆13Aug 22, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆48Dec 4, 2024Updated last year
- Using Software Designed Radio to transmit & receive FM signal☆49Apr 2, 2018Updated 8 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- ☆15Jul 5, 2017Updated 9 years ago
- zynq 7000 series training, with z7-lite board☆22Jun 16, 2022Updated 4 years ago
- Tool to fetch and parse data about Efabless MPW projects☆15Jan 10, 2023Updated 3 years ago
- Voice Recognition using FPGA-Based Neural Networks☆15Jul 6, 2016Updated 10 years ago
- High-level synthesis (HLS) implementation of Sparse Matrix Vector Multiplication☆19Feb 17, 2022Updated 4 years ago
- Open source/hardware SoC plattform based on the lattice mico 32 softcore☆15Apr 10, 2010Updated 16 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆16Apr 11, 2025Updated last year
- ☆16Jun 30, 2025Updated last year
- verilog core for ws2812 leds☆35Nov 3, 2021Updated 4 years ago
- Wireless USB Disk for Pendrive S3☆20Jul 11, 2024Updated 2 years ago
- ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)☆27May 11, 2026Updated 4 months ago
- HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs☆13Feb 9, 2019Updated 7 years ago
- GNURadio implementation of the lazy Viterbi algorithm☆13May 8, 2020Updated 6 years ago