Hello-FPGA / ZYNQ7020_Core_BoardLinks
This is xc7z020clg400 FPGA hardware core board design
☆60Updated last year
Alternatives and similar repositories for ZYNQ7020_Core_Board
Users that are interested in ZYNQ7020_Core_Board are comparing it to the libraries listed below
Sorting:
- Application software for Scopy MVP: FPGA PS, PL, and microcontroller firmware☆75Updated 4 years ago
- xilxin download tools☆53Updated 5 years ago
- Wireless JTAG 'cable' for Xilinx FPGAs. This is an 'English fork' of https://github.com/ciniml/xvc-esp32 project.☆117Updated 4 years ago
- hardware project of a ltc2208 breakout board with simple 2 afe circuit selectalbe☆18Updated 3 years ago
- FTDI EEPROM dumps for common JTAG FPGA programmers☆83Updated last year
- A far more light version anlogic-jtag cable with some enhanced functions.☆51Updated last year
- Audio controller (I2S, SPDIF, DAC)☆89Updated 6 years ago
- fpga jtag hardware☆25Updated 2 years ago
- Simple mono FM Radio.☆48Updated 9 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆72Updated 3 years ago
- ☆40Updated 5 years ago
- Scopy MVP Schematics/Hardware Design Files☆63Updated 4 years ago
- 用于xilinx平台的简易自制下载器。☆98Updated 5 years ago
- Source code of MIPI DSI Bridge Published on https://www.circuitvalley.com☆109Updated last year
- EBAZ4205 BOARD☆206Updated 2 years ago
- FPGA core boards / evaluation boards based on CDCTL hardware☆93Updated 4 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆74Updated 3 years ago
- An ultra-low noise amplifier to measure low-noise LDO/OPA's wide band output noise, and many other interesting measurements. Referred to …☆20Updated 2 years ago
- Digilent JTAG clone hardware + eeprom firmware (.bin)☆68Updated 3 years ago
- SEA-S7_gesture recognition☆17Updated 5 years ago
- Basic USB-CDC device core (Verilog)☆80Updated 4 years ago
- 【例程】国产高云FPGA 开发板及其工程☆36Updated last year
- An open source FPGA design for DSLogic☆165Updated 11 years ago
- FPGA Logic Analyzer and GUI☆139Updated 2 years ago
- FPGA based 30ps RMS TDCs☆86Updated 7 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆52Updated 4 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆56Updated 2 years ago
- USB 2.0 Device IP Core☆69Updated 8 years ago
- ZYNQ7010-20 开源开发板,经济实惠好吃不贵☆160Updated 2 years ago
- 通用IO测试工程,用于捡垃圾测试IO。与BSDL需要对引脚输入不同,该工程只需要确定时钟输入,然后自动向每个IO发送指定字符串,因此只需要将串口接入任意IO查看输出即可☆12Updated 2 months ago