Awais-Asghar / Single-Cycle-RISC-V-Processor-Implemented-on-FPGAView on GitHub
Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).
17Jul 21, 2025Updated 7 months ago

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