Alternatives and similar repositories for 8-point-2D-DCT

Users that are interested in 8-point-2D-DCT are comparing it to the libraries listed below

• viralgokani / 8PointDCT_Verilog
  Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algor…
  ☆23Updated 10 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆127Updated 4 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆104Updated 5 months ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆61Updated 2 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆99Updated 5 years ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆218Updated 7 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆35Updated last year
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆154Updated last year
• gillianGan / ahb_sram_master
  ☆19Updated 5 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆113Updated 10 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆67Updated 5 years ago
• somyadashora / AMBA-AXI4-Lite
  Master and Slave made using AMBA AXI4 Lite protocol.
  ☆26Updated 4 years ago
• hxfycy / 1024-point-fft
  Radix-4 1024 point fft in verilog
  ☆10Updated 5 years ago
• ilaydayaman / CNN_for_SLR
  A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
  ☆95Updated last year
• aiminickwong / H264
  H264视频解码verilog实现
  ☆82Updated 7 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆172Updated 6 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆52Updated 4 years ago
• raiyyanfaisal09 / AHB_APB-RTL
  AHB-APB Bridge RTL Design
  ☆16Updated 7 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 6 years ago
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆180Updated last year
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆60Updated last year
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆48Updated 5 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆137Updated 3 years ago
• yztong / LeNet_RTL
  An LeNet RTL implement onto FPGA
  ☆48Updated 7 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆211Updated 2 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆91Updated last year
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆101Updated 7 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆120Updated 7 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆207Updated last year
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆48Updated 4 years ago