gabrieljcs / ann-vhdl
A HARDWARE IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS FOR INFERENCE
☆30Updated 4 years ago
Alternatives and similar repositories for ann-vhdl:
Users that are interested in ann-vhdl are comparing it to the libraries listed below
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆54Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆160Updated 3 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆80Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆58Updated 2 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆79Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆121Updated 6 years ago
- OpenROAD users should look at this repository first for instructions on getting started☆102Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆54Updated 10 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆37Updated 3 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆33Updated last year
- Verilog digital signal processing components☆126Updated 2 years ago
- OSVVM Documentation☆33Updated this week
- Basic RISC-V Test SoC☆112Updated 5 years ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆26Updated 3 years ago
- Implementing Different Adder Structures in Verilog☆61Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated last month
- Physical Design Flow from RTL to GDS using Opensource tools.☆90Updated 4 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆47Updated 6 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆51Updated this week
- Playing around with Formal Verification of Verilog and VHDL☆54Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆169Updated last week
- Fabric generator and CAD tools☆160Updated last week
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆89Updated 2 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆152Updated this week
- FPGA Design of a Neural Network for Color Detection☆75Updated 2 weeks ago
- ☆130Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆141Updated 8 months ago
- Network on Chip Implementation written in SytemVerilog☆167Updated 2 years ago
- Generic Register Interface (contains various adapters)☆107Updated 4 months ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆143Updated 2 years ago