Alternatives and similar repositories for ann-vhdl

Users that are interested in ann-vhdl are comparing it to the libraries listed below

• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 6 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆186Updated this week
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆173Updated last month
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆128Updated 6 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆97Updated 3 weeks ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆85Updated 6 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆111Updated 2 weeks ago
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆47Updated last year
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆206Updated 10 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆168Updated last week
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆177Updated 5 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆208Updated last week
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆188Updated this week
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆93Updated last year
• akilm / FPU-IEEE-754
  Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…
  ☆55Updated 9 months ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆54Updated 4 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆147Updated 11 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆160Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆79Updated 2 weeks ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 6 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆139Updated last week
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆94Updated last month
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆120Updated 8 months ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆74Updated last year
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆150Updated 3 weeks ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆77Updated last year
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆105Updated last year
• AkeelMedina22 / RISC-V-Pipelined-Processor
  A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
  ☆41Updated 4 years ago