wavedrom / doppler
Doppler effect on WaveForms
☆15Updated last week
Related projects ⓘ
Alternatives and complementary repositories for doppler
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆12Updated 2 years ago
- hardware library for hwt (= ipcore repo)☆34Updated this week
- Public repository for PySysC, (From SC Common Practices Subgroup)☆48Updated 10 months ago
- Cross EDA Abstraction and Automation☆35Updated last week
- A Python to VHDL compiler☆15Updated 2 months ago
- A header only C++11 library for functional coverage☆36Updated 2 years ago
- A tool for merging the MyHDL workflow with Vivado☆19Updated 4 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆21Updated last month
- Provides automation scripts for building BFMs☆16Updated 2 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- A VHDL Core Library.☆17Updated 7 years ago
- Python/Simulator integration using procedure calls☆9Updated 4 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆31Updated 3 weeks ago
- Virtual development board for HDL design☆39Updated last year
- A simple function to add wavedrom diagrams into an ipython notebook.☆22Updated 2 years ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆19Updated this week
- IP-XACT XML binding library☆14Updated 8 years ago
- Python interface for cross-calling with HDL☆23Updated last week
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆47Updated this week
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- cocotb extension for nMigen☆15Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- Generate symbols from HDL components/modules☆20Updated last year
- Open Source Verification Bundle for VHDL and System Verilog☆40Updated 10 months ago
- VHDLproc is a VHDL preprocessor☆24Updated 2 years ago
- This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.☆13Updated this week
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆32Updated last month
- Intel Compiler for SystemC☆23Updated last year