wavedrom / dopplerLinks
Doppler effect on WaveForms
☆17Updated 4 months ago
Alternatives and similar repositories for doppler
Users that are interested in doppler are comparing it to the libraries listed below
Sorting:
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆28Updated 2 months ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Updated 11 months ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆31Updated this week
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- hardware library for hwt (= ipcore repo)☆43Updated 2 weeks ago
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Updated 3 years ago
- WaveDrom compatible python command line☆112Updated 2 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆64Updated 2 years ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 5 years ago
- SLAC Python Based Hardware Abstraction & Data Acquisition System☆48Updated this week
- IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…☆32Updated last year
- Value Change Dump (VCD) parser☆38Updated last year
- Generate address space documentation HTML from compiled SystemRDL input☆60Updated last month
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Updated 3 months ago
- pyVhdl2sch is a python based VHDL to (pdf) schematic converter☆33Updated 6 years ago
- HTML & Js based VCD viewer☆66Updated this week
- An abstract language model of VHDL written in Python.☆59Updated last month
- D3.js based wave (signal) visualizer☆67Updated 4 months ago
- A Python package for testing hardware (part of the magma ecosystem)☆47Updated last year
- Python package for writing Value Change Dump (VCD) files.☆128Updated last year
- Cross EDA Abstraction and Automation☆40Updated last month
- Running Python code in SystemVerilog☆71Updated 7 months ago
- This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.☆20Updated 7 months ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated 2 years ago
- ☆31Updated 2 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆14Updated 5 years ago
- Web-based HDL diagramming tool☆82Updated 2 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆32Updated 2 weeks ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last month
- A header only C++11 library for functional coverage☆36Updated 3 years ago