ska-sa / mlib_develLinks
Matlab/Simulink/XSG tool-flow for developing DSP systems for CASPER hardware
☆17Updated last year
Alternatives and similar repositories for mlib_devel
Users that are interested in mlib_devel are comparing it to the libraries listed below
Sorting:
- ☆58Updated 2 months ago
- Tutorials available here:☆37Updated 3 weeks ago
- Software control for CASPER FPGAs☆17Updated last year
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆42Updated 5 months ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆62Updated 4 years ago
- Simple interface to the Valon 5007 synthesizer.☆13Updated 8 years ago
- Board repo for the ZCU216 RFSOC☆28Updated 2 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆24Updated last year
- Python productivity for RFSoC platforms☆72Updated last year
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆54Updated 3 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆103Updated 2 years ago
- Software that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆24Updated 3 weeks ago
- RFSoC Spectrum Analyser Module on PYNQ.☆79Updated 11 months ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 2 years ago
- 10G Low Latency Ethernet☆54Updated last year
- Repository for FPGA projects☆51Updated 7 months ago
- A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC☆36Updated 8 months ago
- An RFSoC Frequency Planner developed using Python.☆28Updated 2 years ago
- An interactive introduction to the polyphase filterbank technique for radio astronomy spectrometers☆57Updated 4 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆61Updated 3 years ago
- ☆35Updated 5 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 9 months ago
- A testbench for an axi lite custom IP☆23Updated 10 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆32Updated 2 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆49Updated 2 years ago
- migen + misoc + redpitaya = digital servo☆40Updated 6 years ago
- ☆19Updated 3 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆25Updated last year
- IPbus Builder Tool☆13Updated 4 months ago