Alternatives and similar repositories for wbpmic:

Users that are interested in wbpmic are comparing it to the libraries listed below

• ZipCPU / wbpwmaudio
  A wishbone controlled PWM (audio) controller
  ☆17Updated last year
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆40Updated 7 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆49Updated 5 months ago
• olofk / simple_spi
  SPI core
  ☆15Updated 5 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆17Updated 5 months ago
• akukulanski / ADC_Sigma_Delta_VHDL
  Sigma-Delta Analog to Digital Converter in FPGA (VHDL)
  ☆16Updated 7 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• gnuradio / gr-verilog
  ☆16Updated 2 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 4 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆26Updated 4 years ago
• Cognoscan / VerilogCogs
  Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.
  ☆20Updated 9 years ago
• RoaLogic / ahb3lite_timer
  RISC-V compliant Timer IP
  ☆12Updated 11 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• YosysHQ / sby-gui
  GUI for SymbiYosys
  ☆13Updated last year
• ArcaneNibble / project-chibi
  Altera MAX V bitstream documentation -- CLEANUP PENDING
  ☆19Updated 4 years ago
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆29Updated last year
• merledu / symbiflow-magic
  This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.
  ☆10Updated 3 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated 11 months ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆39Updated 9 years ago
• Wren6991 / Hazard3-SWD-SoC
  Example Hazard3 + OpenDAP RISC-V SWD SoC integration
  ☆9Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 4 months ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆31Updated 4 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• ZipCPU / arrowzip
  A ZipCPU based demonstration of the MAX1000 FPGA board
  ☆21Updated 3 years ago
• rprinz08 / arty-s7-multinic
  ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface
  ☆13Updated 4 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated this week
• Digilent / Arty-A7-35-XADC
  ☆19Updated 4 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago