Alternatives and similar repositories for fpga-gpu

Users that are interested in fpga-gpu are comparing it to the libraries listed below

• Kenji-Ishimaru / polyphony
  3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
  ☆85Updated 4 years ago
• zxmarcos / huedeon-gpu
  FPGA GPU design for DE1-SoC
  ☆72Updated 3 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆83Updated 4 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆72Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆94Updated 5 years ago
• bradgrantham / alice5
  SPIR-V fragment shader GPU core based on RISC-V
  ☆40Updated 4 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆83Updated 2 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated last week
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆99Updated last year
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆93Updated 4 years ago
• ChrisPVille / mig_example
  Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
  ☆31Updated 3 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆79Updated last year
• bsc-loca / sargantana
  ☆105Updated 2 months ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆137Updated 6 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆47Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆57Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆64Updated 5 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆107Updated last year
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆125Updated 2 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆140Updated 9 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆49Updated 8 months ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆29Updated 4 years ago
• projf / display_controller
  FPGA display controller with support for VGA, DVI, and HDMI.
  ☆230Updated 5 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 4 years ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated 3 weeks ago