elvizcacho / ReedSolomonLinks
Implementation of a reconfigurable coder and decoder Reed-Solomon on a FPGA
☆10Updated 10 years ago
Alternatives and similar repositories for ReedSolomon
Users that are interested in ReedSolomon are comparing it to the libraries listed below
Sorting:
- DVB-S2 LDPC Decoder☆27Updated 10 years ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- Playground for implementing LDPC codes on FPGA☆16Updated 2 years ago
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆24Updated 5 years ago
- Hardware Viterbi Decoder in verilog☆26Updated 6 years ago
- This project aim is to use the Cypress CYUSB3KIT-003 EZ-USB FX3 SuperSpeed Explorer Kit to both program and communicate with a Xilinx Spa…☆25Updated 3 years ago
- ☆17Updated 2 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Updated 7 years ago
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆48Updated 3 weeks ago
- SDRAM controller for MIPSfpga+ system☆23Updated 4 years ago
- A FPGA accelerated SDR receiver using PYNQ-Z2 board and RTL-SDR☆21Updated 5 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆67Updated 2 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 3 weeks ago
- True Random Number Generator core implemented in Verilog.☆75Updated 4 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- Various projects of SPI loader module for xilinx fpga☆31Updated 4 years ago
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆18Updated last year
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆91Updated 5 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆17Updated 6 months ago
- A collection of phase locked loop (PLL) related projects☆106Updated last year
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆16Updated 7 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 4 years ago
- few python scripts to clone all IP cores from opencores.org☆22Updated last year
- Wi-Fi LDPC codec Verilog IP core☆17Updated 5 years ago
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆21Updated 7 years ago
- I2C Master Verilog module☆34Updated this week
- FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic …☆15Updated 4 years ago