ahmad2smile / SHA256_Verilog
Verilog based FPGA Design of SHA256 Simulated on ModelSim
☆21Updated 7 years ago
Alternatives and similar repositories for SHA256_Verilog
Users that are interested in SHA256_Verilog are comparing it to the libraries listed below
Sorting:
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- UART -> AXI Bridge☆61Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Implementation of the PCIe physical layer☆39Updated 4 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Verilog RTL Design☆37Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆54Updated 4 years ago
- DDR4 Simulation Project in System Verilog☆41Updated 10 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆20Updated 6 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- ☆15Updated 6 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆14Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆68Updated 4 years ago
- USB -> AXI Debug Bridge☆38Updated 3 years ago