ahmad2smile / SHA256_VerilogLinks
Verilog based FPGA Design of SHA256 Simulated on ModelSim
☆21Updated 7 years ago
Alternatives and similar repositories for SHA256_Verilog
Users that are interested in SHA256_Verilog are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆62Updated 4 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆61Updated 4 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- SDRAM controller with AXI4 interface☆97Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- Verilog based BCH encoder/decoder☆123Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 7 months ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 8 months ago
- HW JPEG decoder wrapper with AXI-4 DMA☆35Updated 4 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- DDR4 Simulation Project in System Verilog☆41Updated 11 years ago
- Implementation of the SHA256 Algorithm in Verilog☆37Updated 13 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆18Updated last year
- Verilog RTL Design☆45Updated 4 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- IP operations in verilog (simulation and implementation on ice40)☆58Updated 5 years ago
- ☆78Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- DDR3 SDRAM controller☆18Updated 11 years ago
- ☆36Updated 5 years ago
- ☆64Updated 4 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 7 years ago