efard / DSPHDLLinks
Digital Signal Processing and Well-Known Modulations on HDL
☆41Updated 6 months ago
Alternatives and similar repositories for DSPHDL
Users that are interested in DSPHDL are comparing it to the libraries listed below
Sorting:
- An open-source HDL register code generator fast enough to run in real time.☆76Updated last week
- Playing around with Formal Verification of Verilog and VHDL☆64Updated 4 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 10 months ago
- Drawio => VHDL and Verilog☆61Updated 2 years ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆71Updated 4 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Updated 10 months ago
- A getting started presentation (with examples) about how to use FLOSS for FPGA development.☆36Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- ☆33Updated 2 years ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆25Updated 9 months ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆36Updated 9 months ago
- A flexible and scalable development platform for modern FPGA projects.☆38Updated 2 weeks ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆191Updated 2 weeks ago
- SAR ADC on tiny tapeout☆43Updated 10 months ago
- SpiceBind – spice inside HDL simulator☆56Updated 5 months ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 8 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆81Updated last month
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- ☆110Updated 2 years ago
- IP Core Library - Published and maintained by the Open Source VHDL Group☆43Updated last week
- FuseSoC standard core library☆149Updated 6 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated last week
- FPGA and Digital ASIC Build System☆80Updated 2 weeks ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆25Updated last year
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆70Updated 2 months ago
- Control and Status Register map generator for HDL projects☆128Updated 6 months ago
- Slides and material for Xilinx bootcamp☆22Updated 4 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆64Updated 3 months ago
- A Python package to use FPGA development tools programmatically.☆143Updated 8 months ago