Alternatives and similar repositories for DSPHDL

Users that are interested in DSPHDL are comparing it to the libraries listed below

• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated last week
• rodrigomelo9 / FOSS-for-FPGAs
  A getting started presentation (with examples) about how to use FLOSS for FPGA development.
  ☆36Updated 2 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last year
• suoto / fpga_cores
  ☆33Updated 2 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆52Updated 3 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆61Updated 2 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆65Updated 4 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆39Updated 11 months ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆27Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆119Updated 4 years ago
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆52Updated 2 months ago
• HDLForBeginners / Examples
  ☆118Updated 2 years ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆30Updated last year
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆39Updated last week
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆81Updated this week
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 7 months ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆34Updated 3 weeks ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆73Updated 4 years ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆45Updated last year
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆88Updated 3 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆130Updated 8 months ago
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…
  ☆69Updated 4 months ago
• ldoolitt / vhd2vl
  ☆139Updated 3 weeks ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆197Updated this week
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆74Updated 3 years ago