Alternatives and similar repositories for cadence-skill

Users that are interested in cadence-skill are comparing it to the libraries listed below

• uoyniXnaH / AXL-SKILL
  Cadence Allegro Skills.
  ☆51Updated 6 years ago
• lukeli17 / Allegro_Skill_ziliao
  Cadence Skill资料收集
  ☆25Updated 3 years ago
• ebecheto / Skill
  my cadence/virtuoso/icfb skill functions develloped over the years
  ☆144Updated 2 weeks ago
• unihd-cag / skillbridge
  A seamless python to Cadence Virtuoso Skill interface
  ☆241Updated 9 months ago
• unnir / CadenceSKILL-Python
  Inter Process Communication (IPC) between Python and Cadence Virtuoso
  ☆79Updated 8 years ago
• ananthchellappa / SKILL
  Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.
  ☆51Updated last week
• Gklkrshna / Phase-locked-loop-IC-design
  VSD workshop - Phase Locked Loop(PLL) IC Design
  ☆15Updated 4 years ago
• MatthewLoveQUB / SKILL_Tools
  Utilities for working with Cadence's SKILL/SKILL++ including a unit testing framework.
  ☆44Updated 5 years ago
• FEDEVEL / allegro-script-add_layer_name
  ☆23Updated 8 years ago
• curtisma / VirtuosoToolboxMatlab
  MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System
  ☆30Updated 8 years ago
• cdsgit / cdsgit
  Cadence Virtuoso Git Integration written in SKILL++
  ☆158Updated 3 years ago
• mfilmer / skill
  Useful Cadence skill scripts
  ☆20Updated 6 years ago
• cdsdm / cdsdm
  Cadence Virtuoso Design Management System
  ☆36Updated 3 years ago
• whh5118 / GTOpen
  几楼科技 Cadence Allegro开源项目
  ☆120Updated 5 years ago
• cascode-labs / virtue
  A Python and SKILL Framework for Cadence Virtuoso
  ☆43Updated last week
• Nubis-Communications / SignalIntegrity
  Python tools for signal integrity applications
  ☆160Updated last week
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆126Updated 2 years ago
• KenKundert / psf_utils
  Read Spectre PSF files
  ☆69Updated 2 weeks ago
• trilomix / GDS3D
  GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input …
  ☆237Updated last year
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆67Updated 4 years ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆63Updated this week
• dan-fritchman / Netlist
  Parsing and generating popular formats of circuit netlist
  ☆38Updated 2 years ago
• muhammadaldacher / Analog-Design-of-Asynchronous-SAR-ADC
  This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…
  ☆184Updated last year
• capn-freako / PyBERT
  Serial communication link bit error rate tester simulator, written in Python.
  ☆117Updated 3 weeks ago
• muhammadaldacher / RF-design-of-1.9-GHz-Rx-frontend
  This project shows the design process of the main blocks of a typical RX frontend system.
  ☆25Updated 4 years ago
• jamieiles / uart
  Verilog UART
  ☆186Updated 12 years ago
• shinde-shantanu / FPGA_TDC
  Time to Digital Converter on an FPGA
  ☆14Updated 5 years ago
• charkster / spi_slave_verilog
  SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
  ☆17Updated 5 years ago
• Werni2A / OpenOrCadParser
  OpenOrCadParser - FOSS Parser for Cadence OrCAD designs.
  ☆65Updated last year
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 2 years ago