Alternatives and similar repositories for ImpeccableCircuits

Users that are interested in ImpeccableCircuits are comparing it to the libraries listed below

• FPGA-Research / FPGAVirusScanner
  Program to scan for malicious FPGA designs.
  ☆14Updated 4 years ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆35Updated last month
• colinoflynn / xdomain-dpa-m23
  Cross-Domain DPA Attack on SAML11
  ☆16Updated 6 years ago
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆30Updated last year
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆37Updated 4 months ago
• Chair-for-Security-Engineering / AES_masked_BRAM
  Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
  ☆16Updated 4 years ago
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆34Updated last year
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• ChairImpSec / PROLEAD
  PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software
  ☆40Updated 3 weeks ago
• ikizhvatov / pysca
  Toolbox for advanced differential power analysis of symmetric key cryptographic algorithm implementations
  ☆49Updated 6 years ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated last year
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• ultraembedded / riscv_sbc
  A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
  ☆29Updated 5 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆106Updated 2 months ago
• 0xADE1A1DE / Rosita
  ☆17Updated 2 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆22Updated 3 years ago
• fm4dd / gatemate-riscv
  RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga
  ☆12Updated 4 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 6 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• rprimas / ascon-verilog
  Hardware Design of Ascon
  ☆23Updated 3 weeks ago
• GMUCERG / LWC
  Development Package for the Hardware API for Lightweight Cryptography
  ☆16Updated 3 months ago
• secworks / blake2s
  Verilog implementation of the 32-bit version of the Blake2 hash function
  ☆21Updated 3 months ago
• sca-research / GILES
  ☆12Updated 3 years ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆22Updated 9 months ago
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆19Updated last year
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• incoresemi / river_core
  RiVer Core is an open source Python based RISC-V Core Verification framework.
  ☆22Updated last month