Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
☆16May 29, 2020Updated 6 years ago
Alternatives and similar repositories for RV32IC-CPU
Users that are interested in RV32IC-CPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…☆22Apr 13, 2023Updated 3 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- Educational 16-bit MIPS Processor☆18Feb 16, 2019Updated 7 years ago
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆22Nov 9, 2025Updated 7 months ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 4 years ago
- Petri Net Simulator program☆10Nov 27, 2017Updated 8 years ago
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- Simodense: a RISC-V softcore for custom SIMD instructions☆17Feb 16, 2026Updated 4 months ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆21Feb 16, 2024Updated 2 years ago
- Radix-4 1024 point fft in verilog☆12Apr 29, 2020Updated 6 years ago
- ☆17Oct 20, 2025Updated 7 months ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆149Dec 2, 2019Updated 6 years ago
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆12Dec 26, 2024Updated last year
- Lattice-Based Post-Quantum Authenticated Key Exchange☆22May 19, 2017Updated 9 years ago
- Short proof-of-concepts for STM32 boards using a very minimal interface☆18Jan 29, 2018Updated 8 years ago
- ☆21Jun 2, 2017Updated 9 years ago
- Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predict…☆15Oct 9, 2017Updated 8 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 2 years ago
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆13May 6, 2026Updated last month
- 16-Point FFT is developed in order to accurately model that of the MATLAB function. . The module successfully tested using verilog testbe…☆19May 27, 2016Updated 10 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- LSTM neural network (verilog)☆16Dec 5, 2018Updated 7 years ago
- ☆22May 29, 2026Updated 2 weeks ago
- Cryptonight Monero Verilog code for ASIC☆20Mar 29, 2018Updated 8 years ago
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆12Dec 6, 2023Updated 2 years ago
- ☆12Feb 12, 2026Updated 4 months ago
- Latest PyTorch Implementation of DeltaGRU & DeltaLSTM that Exploits Temporal Sparsity in Sequential Data☆17Sep 30, 2023Updated 2 years ago
- RISC-V Instruction Set Metadata☆42Oct 21, 2018Updated 7 years ago
- C++ framework for easier interaction with OpenGL code☆20Mar 24, 2013Updated 13 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- AI assisted Shell, aka "Ash". Wraps around your existing shell and brings AI-LLM to the CLI for analyzing EDA files.☆28Apr 6, 2026Updated 2 months ago
- FPT: a Fixed-Point Accelerator for Torus Fully Homomorphic Encryption☆30Sep 2, 2025Updated 9 months ago
- ☆12Updated this week
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17May 26, 2021Updated 5 years ago
- MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.☆25Oct 3, 2018Updated 7 years ago
- Resource Utilization and Latency Estimation for ML on FPGA.☆19Apr 11, 2026Updated 2 months ago
- PCI Express ® Base Specification Revision 3.0☆13May 23, 2018Updated 8 years ago