MauererM / VIIRF
Hardware description (VHDL) and configuration scripts (Python) of a versatile IIR Filter implemented as cascaded SOS/biquads. No vendor-specific hardware constructs used.
☆19Updated 6 years ago
Alternatives and similar repositories for VIIRF:
Users that are interested in VIIRF are comparing it to the libraries listed below
- VHDL Library for implementing common DSP functionality.☆27Updated 6 years ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆32Updated this week
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- Small footprint and configurable JESD204B core☆40Updated 3 weeks ago
- VHDL Modules☆23Updated 9 years ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- Extensible FPGA control platform☆56Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆42Updated 3 years ago
- VHDL PCIe Transceiver☆26Updated 4 years ago
- general-cores☆18Updated 4 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆30Updated 3 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 5 months ago
- This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals☆19Updated last year
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆42Updated 3 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆79Updated last year
- A testbench for an axi lite custom IP☆23Updated 10 years ago
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆55Updated 4 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆108Updated 3 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆59Updated 2 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆22Updated 6 months ago
- This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…☆64Updated 7 years ago
- Connecting FPGA and MCU using Ethernet RMII☆22Updated 9 years ago
- VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and …☆22Updated last week
- DPLL for phase-locking to 1PPS signal☆28Updated 8 years ago
- Triple Modular Redundancy☆24Updated 5 years ago