Alternatives and similar repositories for libposit:

Users that are interested in libposit are comparing it to the libraries listed below

• cliffordwolf / bextdep
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆24Updated 7 years ago
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆37Updated this week
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆21Updated 8 years ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆31Updated 2 weeks ago
• Mogball / declarative-mlir-compiler
  Declarative MLIR compilers in Python!
  ☆33Updated 4 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆69Updated 5 years ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆38Updated 2 years ago
• oprecomp / flexfloat
  C library for the emulation of reduced-precision floating point types
  ☆48Updated 2 years ago
• eruffaldi / cppPosit
  c++ posit implementation
  ☆44Updated last year
• ychen306 / vegen
  ☆28Updated 2 years ago
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆38Updated last year
• fpgasystems / fpga-hyperloglog
  FPGA-based HyperLogLog Accelerator
  ☆12Updated 4 years ago
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆33Updated last month
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆39Updated 2 weeks ago
• IntelLabs / t2sp
  Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)
  ☆31Updated 10 months ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated 3 weeks ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆52Updated this week
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 4 years ago
• SamuelBayliss / Potholes
  Polyhedral Compilation tool for High Level Synthesis.
  ☆10Updated 10 years ago
• pulp-platform / redmule
  ☆53Updated this week
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• vegaluisjose / reticle
  ☆40Updated 3 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆32Updated 10 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆54Updated 6 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆41Updated 11 months ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆74Updated 6 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 2 weeks ago