cjdelisle / libpositLinks
A library for working with the posit number type.
☆15Updated 4 years ago
Alternatives and similar repositories for libposit
Users that are interested in libposit are comparing it to the libraries listed below
Sorting:
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆25Updated 7 years ago
- c++ posit implementation☆44Updated 2 years ago
- A powerful and modern open-source architecture description language.☆42Updated 7 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- FPGA Assembly (FASM) Parser and Generator☆95Updated 3 years ago
- The SiFive wake build tool☆91Updated this week
- Gatery, a library for circuit design.☆20Updated 8 months ago
- Gate-Level Simulation on a GPU☆10Updated 8 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆29Updated this week
- A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…☆28Updated 8 months ago
- A standard for floating point accuracy benchmarks☆52Updated 4 months ago
- materials available to the public☆27Updated last week
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 4 years ago
- C++ command shell library☆53Updated 10 months ago
- The J1 CPU☆171Updated 4 years ago
- A hardware-optimized high-quality pseudorandom number generator☆36Updated last month
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- domain-level nucleic acid reaction enumeration☆9Updated last year
- Declarative MLIR compilers in Python!☆35Updated 4 years ago
- Initialize / Fill C++ array fast - O(1) time with only 1 extra bit of memory.☆30Updated 2 years ago
- Library to plot integer sets and maps☆50Updated 8 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Lace - implementation of work-stealing in C☆52Updated this week
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- TestFloat release 3☆64Updated 5 months ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- Visual Simulation of Register Transfer Logic☆99Updated 5 months ago
- Beyond Floating Point - Posit C/C++ implementation☆296Updated last year
- A reconfigurable and extensible VLIW processor implemented in VHDL☆34Updated 10 years ago