Alternatives and similar repositories for xormix

Users that are interested in xormix are comparing it to the libraries listed below

• suarezvictor / CflexHDL
  Design digital circuits in C. Simulate really fast with a regular compiler.
  ☆174Updated 2 weeks ago
• olofk / corescore
  CoreScore
  ☆168Updated 2 weeks ago
• JulianKemmerer / PipelineC-Graphics
  Graphics demos
  ☆112Updated last year
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 7 months ago
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆222Updated last year
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆87Updated 6 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆62Updated last year
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆186Updated last month
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 10 months ago
• mrisc32 / mc1
  A computer (FPGA SoC) based on the MRISC32-A1 CPU
  ☆54Updated 2 years ago
• tomverbeure / rt
  A Full Hardware Real-Time Ray-Tracer
  ☆109Updated 2 weeks ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆74Updated this week
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆97Updated last year
• nickmqb / wyre
  Hardware definition language that compiles to Verilog
  ☆106Updated 4 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• TinyTapeout / vga-playground
  Playground for VGA projects on Tiny Tapeout
  ☆66Updated 2 weeks ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆73Updated 3 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 5 months ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated last week
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆106Updated 3 months ago
• smunaut / doom_riscv
  Doom classic port to lightweight RISC‑V
  ☆100Updated 3 years ago
• ecilasun / tinysys
  A tiny system built on a small QMTECH board
  ☆110Updated 7 months ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆30Updated 2 weeks ago
• aappleby / metron
  A C++ to Verilog translation tool with some basic guarantees that your code will work.
  ☆175Updated 9 months ago
• sifiveinc / wake
  The SiFive wake build tool
  ☆91Updated this week
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆139Updated 2 years ago
• olofk / vidbo
  Virtual Development Board
  ☆64Updated 4 years ago
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆50Updated last month