MaartenBaert / xormixLinks
A hardware-optimized high-quality pseudorandom number generator
☆36Updated 3 weeks ago
Alternatives and similar repositories for xormix
Users that are interested in xormix are comparing it to the libraries listed below
Sorting:
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆220Updated last year
- Graphics demos☆110Updated last year
- Design digital circuits in C. Simulate really fast with a regular compiler.☆174Updated 2 years ago
- CoreScore☆158Updated 5 months ago
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆86Updated 5 years ago
- A C++ to Verilog translation tool with some basic guarantees that your code will work.☆171Updated 4 months ago
- Yet Another VHDL tool☆31Updated 8 years ago
- A bit-serial CPU written in VHDL, with a simulator written in C.☆127Updated 10 months ago
- Example LED blinking project for your FPGA dev board of choice☆178Updated last month
- Demo SoC for SiliconCompiler.☆59Updated last month
- Exploring gate level simulation☆58Updated 2 months ago
- Reusable Verilog 2005 components for FPGA designs☆45Updated 4 months ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆28Updated last week
- FPGA based microcomputer sandbox for software and RTL experimentation☆62Updated last week
- Hardware definition language that compiles to Verilog☆106Updated 3 years ago
- The SiFive wake build tool☆90Updated this week
- A Verilog Synthesis Regression Test☆37Updated last year
- A pipelined RISC-V processor☆57Updated last year
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- ☆79Updated last year
- A computer (FPGA SoC) based on the MRISC32-A1 CPU☆56Updated last year
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- A Full Hardware Real-Time Ray-Tracer☆107Updated 2 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆95Updated last month
- Experiments with Yosys cxxrtl backend☆49Updated 6 months ago
- A tiny system built on a small QMTECH board☆107Updated 3 months ago
- Documenting Lattice's 28nm FPGA parts☆143Updated last year
- The J1 CPU☆169Updated 4 years ago
- A modern schematic entry and simulation program☆70Updated last week