Alternatives and similar repositories for Public:

Users that are interested in Public are comparing it to the libraries listed below

• makslevental / mmlir
  A minimal (really) out-of-tree MLIR example
  ☆40Updated 2 months ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆41Updated 3 months ago
• llvm / eudsl
  Embedded Universal DSL: a good DSL for us, by us
  ☆32Updated this week
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆30Updated this week
• mwillsey / cs265
  Website for CS 265
  ☆28Updated 2 months ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆40Updated 10 months ago
• riscv / riscv-bfloat16
  ☆33Updated 7 months ago
• wpmed92 / shaderpulse
  A GLSL compiler targeting SPIR-V mlir
  ☆16Updated 4 months ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆103Updated 3 weeks ago
• hlslibs / ac_types
  Algorithmic C Datatypes
  ☆121Updated 2 months ago
• MPACT-ORG / mpact-compiler
  Retargetable ML compilers for the twenty-first century!
  ☆12Updated 5 months ago
• gvsoc / gvsoc
  ☆16Updated this week
• Mogball / declarative-mlir-compiler
  Declarative MLIR compilers in Python!
  ☆33Updated 4 years ago
• pnnl / COMET
  ☆40Updated this week
• kumasento / polymer
  Bridging polyhedral analysis tools to the MLIR framework
  ☆108Updated last year
• openhwgroup / corev-llvm-project
  ☆13Updated 7 months ago
• ychen306 / vegen
  ☆28Updated 2 years ago
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆45Updated this week
• Meinersbur / isl
  Integer Set Library (source repository: http://repo.or.cz/w/isl.git)
  ☆67Updated last month
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated this week
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆36Updated 11 months ago
• makslevental / mlir-python-extras
  The missing pieces (as far as boilerplate reduction goes) of the upstream MLIR python bindings.
  ☆82Updated this week
• intel / vc-intrinsics
  ☆56Updated last week
• makslevental / nelli
  A lightweight, Pythonic, frontend for MLIR
  ☆80Updated last year
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆142Updated last year
• nod-ai / PI
  A lightweight MLIR Python frontend with support for PyTorch
  ☆23Updated 6 months ago
• camel-cdr / rvv-bench-results
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
  ☆28Updated 2 months ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆35Updated 3 years ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆28Updated this week
• tobiasgrosser / islplot
  Library to plot integer sets and maps
  ☆49Updated 8 years ago