Alternatives and similar repositories for Public

Users that are interested in Public are comparing it to the libraries listed below

• artecs-group / PERCIVAL
  Open-Source Posit RISC-V Core with Quire Capability
  ☆69Updated last year
• sifiveinc / wake
  The SiFive wake build tool
  ☆92Updated this week
• ucb-bar / berkeley-testfloat-3
  TestFloat release 3
  ☆73Updated 11 months ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆54Updated last month
• MPACT-ORG / mpact-compiler
  Retargetable ML compilers for the twenty-first century!
  ☆13Updated 9 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆40Updated 6 months ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆141Updated 2 weeks ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆99Updated 3 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated last month
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆50Updated last year
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆148Updated last month
• riscvarchive / riscv-code-size-reduction
  ☆148Updated last year
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆45Updated 10 months ago
• makslevental / mmlir
  A minimal (really) out-of-tree MLIR example
  ☆46Updated 5 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆95Updated last year
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆131Updated 4 months ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆76Updated 6 years ago
• openhwgroup / corev-llvm-project
  ☆18Updated last year
• camel-cdr / rvv-bench-results
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
  ☆45Updated last week
• FPBench / FPBench
  A standard for floating point accuracy benchmarks
  ☆58Updated 3 weeks ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆157Updated this week
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 4 years ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆49Updated 8 years ago
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆193Updated last month
• tenstorrent / whisper
  ☆78Updated this week
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆84Updated 2 weeks ago
• hlslibs / ac_types
  Algorithmic C Datatypes
  ☆133Updated last month
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆31Updated last week
• llvm / eudsl
  Embedded Universal DSL: a good DSL for us, by us
  ☆66Updated last week