☆21Mar 19, 2024Updated 2 years ago
Alternatives and similar repositories for ideas
Users that are interested in ideas are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VUnit and Cocotb Smashed Together☆16May 31, 2024Updated 2 years ago
- Tapeouts done using OpenFASOC☆22Nov 3, 2025Updated 10 months ago
- ICCAD-2021-B☆12Aug 5, 2021Updated 5 years ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆27Mar 5, 2025Updated last year
- ☆13Jan 25, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Tensor Processing Unit implementation in Verilog☆16Aug 12, 2026Updated 3 weeks ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆13Jul 14, 2024Updated 2 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 5 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- ☆16May 6, 2026Updated 4 months ago
- ☆16Apr 8, 2023Updated 3 years ago
- A template-based, layer-oriented High Level Synthesis Tool for AI algorithms☆15Jul 20, 2026Updated last month
- This is a SpyDrNet Plugin for a physical design related transformations☆16Updated this week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- This repo is created to include illustrative examples on object oriented design pattern in SV☆62Feb 25, 2023Updated 3 years ago
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆26Jun 25, 2018Updated 8 years ago
- ☆12Jul 3, 2020Updated 6 years ago
- Project ideas list for Google Summer of Code.☆18Jan 28, 2026Updated 7 months ago
- Standard and Curated cores, tested and working.☆11Dec 29, 2022Updated 3 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆34Feb 6, 2020Updated 6 years ago
- [CVPRW'22] A privacy attack that exploits Adversarial Training models to compromise the privacy of Federated Learning systems.☆12Jul 7, 2022Updated 4 years ago
- Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7☆11May 25, 2024Updated 2 years ago
- cocotb code library☆13Dec 28, 2020Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- Sick Codes AUR Packages☆10Nov 8, 2023Updated 2 years ago
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- TUM EI7402 SystemC laboratory assignments☆11Aug 10, 2021Updated 5 years ago
- This document is a project of cmos image sensor system. The doc mainly includes LUPA4000 Cmos sensor driving, SDRAM storage, LVDS data re…☆13Feb 7, 2021Updated 5 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆19Jul 21, 2020Updated 6 years ago
- Examples from the Openlane repository, adapted as Fusesoc cores☆12May 18, 2021Updated 5 years ago
- Real-Time Image Processing for ASIC/FGPA☆27Feb 23, 2022Updated 4 years ago
- ☆10Jan 15, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆19Dec 5, 2022Updated 3 years ago
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆21Apr 12, 2026Updated 4 months ago
- My configuration files☆10Updated this week
- This repository provides a Linux kernel driver for AXI UART Lite accessed via PCIe XDMA. It enables efficient DMA-based UART communicatio…☆16May 2, 2025Updated last year
- A Single Cycle Risc-V 32 bit CPU☆78Jan 14, 2026Updated 7 months ago
- Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more☆18Apr 3, 2025Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 5 years ago