angrave / CS241-Lectures-SP22Links
☆8Updated 3 years ago
Alternatives and similar repositories for CS241-Lectures-SP22
Users that are interested in CS241-Lectures-SP22 are comparing it to the libraries listed below
Sorting:
- An open-source quantum automatic test generator.☆14Updated 2 weeks ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆12Updated 11 years ago
- Routing Visualization for Physical Design☆19Updated 6 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- 張耀文老師的"奈米積體電路實體設計"作業(Physical Design)☆8Updated last year
- Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”☆12Updated last year
- This is an implemention of Lee-Moore's Shortest Path Maze Router with multi-sink nets support.☆13Updated 9 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- ☆12Updated 9 years ago
- Some simple examples for the Magic VLSI physical chip layout tool.☆30Updated 4 years ago
- Logic Synthesis and Verification: Programming Assignments☆13Updated 6 months ago
- Tutorial on building your own CPU, in Verilog☆33Updated 3 years ago
- Simulated Annealing to minimize the wirelength☆8Updated 8 years ago
- Architecting and Building High Speed SoCs, published by Packt☆29Updated 2 years ago
- ☆21Updated last year
- This Repo is meant and maintained to help learners complete the course -- "C-for-Everyone-Programming-Fundamentals-by-University-of-Calif…☆16Updated 4 years ago
- CMake based hardware build system☆27Updated last week
- ☆59Updated 3 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- This repository contains the verilog code files of Single Cycle RISC-V architecture☆33Updated 5 years ago
- Open source EDA chip design flow☆51Updated 8 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆103Updated 4 years ago
- C++ command shell library☆53Updated 8 months ago
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆37Updated 4 years ago
- VHDL code examples for a digital design course☆21Updated 5 years ago
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆22Updated 4 years ago
- ☆15Updated 4 years ago
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆16Updated 3 years ago
- RISCV CPU implementation in SystemVerilog☆27Updated 8 months ago
- My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition …☆24Updated 2 years ago