Alternatives and similar repositories for RISC_V_Single_Cycle_Processor:

Users that are interested in RISC_V_Single_Cycle_Processor are comparing it to the libraries listed below

• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆33Updated last year
• merldsu / RISCV_Pipeline_Core
  This repository contains the design files of RISC-V Pipeline Core
  ☆35Updated last year
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆26Updated 3 years ago
• AkeelMedina22 / RISC-V-Pipelined-Processor
  A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
  ☆26Updated 3 years ago
• vinayrayapati / iiitb_rv32i
  ☆13Updated 2 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆80Updated last year
• adibis / Interrupt_Controller
  An 8 input interrupt controller written in Verilog.
  ☆25Updated 12 years ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆23Updated 3 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆38Updated 7 months ago
• merldsu / SAP_FPU
  This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.
  ☆18Updated last year
• Marco-Winzker / NN_RGB_FPGA
  FPGA Design of a Neural Network for Color Detection
  ☆75Updated 2 weeks ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆89Updated 4 years ago
• akilm / FPU-IEEE-754
  Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…
  ☆48Updated 6 months ago
• 4a1c0 / RV32i-Verilog
  Simple RiscV core for academic purpose.
  ☆22Updated 4 years ago
• tianrenz2 / Single-Cycle-Processor
  Single-Cycle RISC-V Processor in systemverylog
  ☆20Updated 5 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆39Updated 6 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆62Updated 2 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆58Updated 2 months ago
• sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog
  Single Cycle RISC MIPS Processor
  ☆32Updated 3 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆97Updated 9 months ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆65Updated last year
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆123Updated 5 years ago
• neeraj1397 / Physical-Design-With-OpenLANE-and-SKY130
  This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://ww…
  ☆16Updated 2 years ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆28Updated 3 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆80Updated 5 years ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆121Updated 3 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆29Updated 5 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆39Updated 4 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated this week