govardhnn / RISC_V_Single_Cycle_Processor

Related projects ⓘ

Alternatives and complementary repositories for RISC_V_Single_Cycle_Processor

• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆29Updated 11 months ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆25Updated 3 years ago
• vinayrayapati / iiitb_rv32i
  ☆13Updated 2 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆32Updated 4 months ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆60Updated 5 years ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆55Updated 10 months ago
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆34Updated 5 months ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆118Updated 4 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆59Updated last month
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆71Updated 5 years ago
• gju06051 / TPU_HW_Verilog
  ☆12Updated last year
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆74Updated 4 years ago
• sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog
  Single Cycle RISC MIPS Processor
  ☆30Updated 3 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆21Updated 2 years ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆28Updated 3 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆18Updated 3 years ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆83Updated 3 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆86Updated 4 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆49Updated 2 years ago
• merldsu / RISCV_Pipeline_Core
  This repository contains the design files of RISC-V Pipeline Core
  ☆34Updated last year
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆63Updated last year
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆26Updated 7 months ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆22Updated 3 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆36Updated 5 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆83Updated 4 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆36Updated 4 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆39Updated 4 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆127Updated 5 months ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆25Updated this week