Alternatives and similar repositories for LSV-PA

Users that are interested in LSV-PA are comparing it to the libraries listed below

• ByronHsu / FRAIGs
  C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.
  ☆10Updated 4 years ago
• NTU-LaDS-II / qATG
  An open-source quantum automatic test generator.
  ☆14Updated 2 weeks ago
• asfhiolNick / NTU_PhysicalDesign_201902
  張耀文老師的"奈米積體電路實體設計"作業(Physical Design)
  ☆8Updated last year
• Daikon-Sun / Routing-Visualization
  Routing Visualization for Physical Design
  ☆19Updated 6 years ago
• lsils / mockturtle
  C++ logic network library
  ☆231Updated last week
• msoeken / cirkit
  A circuit toolkit
  ☆101Updated 5 years ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆194Updated last year
• gmeuli / caterpillar
  ☆25Updated 4 years ago
• nbulsi / also
  A logic synthesis tool
  ☆73Updated last month
• msoeken / kitty
  C++ truth table library
  ☆55Updated last year
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆120Updated last week
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆191Updated 8 months ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆76Updated last month
• Daikon-Sun / Physical-Design-for-Nanometer-ICs
  Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
  ☆41Updated 6 years ago
• ABKGroup / TritonRoute-WXL
  ☆30Updated 4 years ago
• lnis-uofu / ML-Mapper
  ☆11Updated 2 years ago
• marcelwa / aigverse
  A Python library for working with logic networks, synthesis, and optimization.
  ☆17Updated this week
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆28Updated 5 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆73Updated 7 years ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆19Updated last month
• panhomyoung / phySAT
  Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.
  ☆15Updated last year
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆27Updated 5 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆135Updated 2 years ago
• ycunxi / FLowGen-CNNs-DAC18
  ☆14Updated 7 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆30Updated 10 months ago
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆13Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆54Updated last year
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆18Updated last month
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago