Alternatives and similar repositories for cpu-tutorial

Users that are interested in cpu-tutorial are comparing it to the libraries listed below

• rafaelcalcada / rvx
  RISC-V soft-core microcontroller for FPGA implementation
  ☆184Updated last week
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆197Updated 3 years ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆430Updated last week
• lightcode / 8bit-computer
  A simple 8-bit computer build in Verilog.
  ☆68Updated 4 months ago
• ejrh / cpu
  A very primitive but hopefully self-educational CPU in Verilog
  ☆149Updated 10 years ago
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆56Updated last year
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆75Updated last month
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆119Updated 3 weeks ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 11 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆152Updated 5 months ago
• digital-design-hq / Digital-Resources
  ☆61Updated 3 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆113Updated last year
• johnwinans / rvalp
  RISC-V Assembly Language Programming
  ☆240Updated last year
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆219Updated 5 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆302Updated 8 months ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆95Updated 7 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated last year
• RoaLogic / RV12
  RISC-V CPU Core
  ☆389Updated 4 months ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆110Updated last year
• jaywonchung / Verilog-Harvard-CPU
  Verilog implementation of various types of CPUs
  ☆64Updated 6 years ago
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆224Updated 4 years ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆134Updated 4 years ago
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆261Updated 9 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆279Updated last year
• wuhanstudio / nand2tetris-iverilog
  A 16-bit Hack CPU from scratch on FPGA.
  ☆59Updated 4 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 7 years ago
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆75Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 3 months ago
• os-fpga / Virtual-FPGA-Lab
  This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…
  ☆224Updated 4 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆98Updated this week