This a complete and fully working Viola-Jones face detection algorithm described in VHDL and verified on the DE2-115 FPGA board.
☆48Feb 22, 2017Updated 9 years ago
Alternatives and similar repositories for Face-Detection-on-FPGA
Users that are interested in Face-Detection-on-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Gesture Recognition Based on ALTERA DE2-115 FPGA☆12Mar 18, 2014Updated 12 years ago
- Hardware interface for USB controller on DE2 FPGA Platform☆27Dec 24, 2021Updated 4 years ago
- This repository includes some FPGA projects like VGA control, image processing. So far, fpga can drive a VGA monitor and display an image…☆14Jul 5, 2017Updated 9 years ago
- Space invaders hardware clone on the DE2-115 FPGA dev board with a USB keyboard and VGA output.☆13Feb 16, 2020Updated 6 years ago
- Modulation and Arbitrary Waveform Generator☆20Feb 16, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆17Oct 3, 2016Updated 9 years ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆11Nov 16, 2024Updated last year
- Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images☆73Nov 2, 2021Updated 4 years ago
- A RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 …☆32Mar 18, 2023Updated 3 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆39May 20, 2026Updated 3 months ago
- OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verificati…☆16Aug 24, 2026Updated last week
- ☆26May 16, 2024Updated 2 years ago
- Implementation of Sobel Filter in Verilog☆29Mar 10, 2017Updated 9 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- MPU6050 interface for fpga☆11May 9, 2020Updated 6 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆195Jul 28, 2021Updated 5 years ago
- WM8731 Audio CODEC using Verilog (DE2-115)☆11Jul 28, 2019Updated 7 years ago
- Mandelbrot Set in VHDL targetting the Cyclone IVE found on a DE2-115 board.☆11May 2, 2013Updated 13 years ago
- ☆23Oct 20, 2023Updated 2 years ago
- 机器人使用了Xilinx的SPARTAN-6系列芯片以及ISE设计工具对机器人控制电路进行了设计和仿真,验证了电路的正确性和可靠性。同时机器人使用了温湿度传感器、人体感应传感器、超声波传感器、震动传感器、有毒气体传感器等,可以对灾区的环境和受困人员进行多方面的检测和响应。还…☆11Nov 15, 2023Updated 2 years ago
- Open Source Projects from Pallas Lab☆21Oct 10, 2021Updated 4 years ago
- Nexys 4 DDR Artix-7☆11Jun 15, 2018Updated 8 years ago
- plot Multiple Sequence Alignment(MSA) of Clustal by python package☆15Mar 14, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This project aims to implement a full SDRAM controller for Altera DE2-115 FPGA☆14Nov 24, 2014Updated 11 years ago
- ☆11Sep 23, 2022Updated 3 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆16May 17, 2024Updated 2 years ago
- This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to buil…☆44Feb 17, 2019Updated 7 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆39Dec 24, 2020Updated 5 years ago
- HW and SW based implementation of Canny Edge Detection Algorithm.☆12Jan 15, 2018Updated 8 years ago
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆15May 3, 2012Updated 14 years ago
- Custom Altera FPGA designs by Olaoluwa Raji. This repository contains numerous projects that were successfully implemented on an Altera C…☆22Jun 22, 2026Updated 2 months ago
- This repository contains all the needed source files for several examples from Pong Chu's book: "Pong P. Chu, FPGA Prototyping by VHDL Ex…☆11Apr 2, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predict…☆15Oct 9, 2017Updated 8 years ago
- Gender Detection From Facial Features using various methods like Eigenfaces,K-means,PCA then SVM☆11Dec 14, 2016Updated 9 years ago
- ECE563 Final Project - FPGA based camera tracking☆18Dec 17, 2013Updated 12 years ago
- library and CLI tool that merges multiple Test Anything Protocol streams☆13Nov 21, 2019Updated 6 years ago
- Design & Implementation of Multi Clock Domain System using Verilog HDL☆13Oct 4, 2023Updated 2 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 8 years ago