This a complete and fully working Viola-Jones face detection algorithm described in VHDL and verified on the DE2-115 FPGA board.
☆48Feb 22, 2017Updated 9 years ago
Alternatives and similar repositories for Face-Detection-on-FPGA
Users that are interested in Face-Detection-on-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Gesture Recognition Based on ALTERA DE2-115 FPGA☆12Mar 18, 2014Updated 12 years ago
- Hardware interface for USB controller on DE2 FPGA Platform☆27Dec 24, 2021Updated 4 years ago
- ☆45Mar 21, 2020Updated 6 years ago
- This repository includes some FPGA projects like VGA control, image processing. So far, fpga can drive a VGA monitor and display an image…☆14Jul 5, 2017Updated 8 years ago
- Modulation and Arbitrary Waveform Generator☆20Feb 16, 2021Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆18Oct 3, 2016Updated 9 years ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆11Nov 16, 2024Updated last year
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆11Mar 12, 2021Updated 5 years ago
- Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images☆69Nov 2, 2021Updated 4 years ago
- Open Source Projects from Pallas Lab☆21Oct 10, 2021Updated 4 years ago
- Image capture, image filtering and image display (VGA) : picture in picture, edge detection, gray image and smooth image☆76Mar 8, 2014Updated 12 years ago
- ☆27Nov 2, 2017Updated 8 years ago
- OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verificati…☆14Jun 6, 2026Updated last week
- ☆26May 16, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- This repository contains FPGA code for various projects like Lighthouse Tracking as well as some IP cores. The repository is board-indepe…☆14Sep 8, 2021Updated 4 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆185Jul 28, 2021Updated 4 years ago
- ☆24Oct 20, 2023Updated 2 years ago
- MPU6050 interface for fpga☆11May 9, 2020Updated 6 years ago
- Nexys 4 DDR Artix-7☆11Jun 15, 2018Updated 8 years ago
- 机器人使用了Xilinx的SPARTAN-6系列芯片以及ISE设计工具对机器人控制电路进行了设计和仿真,验证了电路的正确性和可靠性。同时机器人使用了温湿度传感器、人体感应传感器、超声波传感器、震动传感器、有毒气体传感器等,可以对灾区的环境和受困人员进行多方面的检测和响应。还…☆11Nov 15, 2023Updated 2 years ago
- Mandelbrot Set in VHDL targetting the Cyclone IVE found on a DE2-115 board.☆11May 2, 2013Updated 13 years ago
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆15May 3, 2012Updated 14 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆11Sep 23, 2022Updated 3 years ago
- Hardware implementation of the SipHash short-inout PRF☆17Apr 3, 2025Updated last year
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆48Apr 22, 2024Updated 2 years ago
- WM8731 Audio CODEC using Verilog (DE2-115)☆11Jul 28, 2019Updated 6 years ago
- Radix-4 1024 point fft in verilog☆12Apr 29, 2020Updated 6 years ago
- An IEEE 802.11b physical layer prototype on Gnuradio & USRP☆33Jun 7, 2026Updated last week
- This project aims to implement a full SDRAM controller for Altera DE2-115 FPGA☆14Nov 24, 2014Updated 11 years ago
- HW and SW based implementation of Canny Edge Detection Algorithm.☆12Jan 15, 2018Updated 8 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆19Feb 20, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This repository contains synthesizable examples which use the PoC-Library.☆39Dec 24, 2020Updated 5 years ago
- Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predict…☆15Oct 9, 2017Updated 8 years ago
- Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerat…☆11Dec 13, 2019Updated 6 years ago
- OpenAI-compatible HTTP server for OmniVoice text-to-speech☆64Jun 8, 2026Updated last week
- Design & Implementation of Multi Clock Domain System using Verilog HDL☆13Oct 4, 2023Updated 2 years ago
- Signal generator designed with Nexy4 FPGA☆13May 14, 2023Updated 3 years ago
- ECE563 Final Project - FPGA based camera tracking☆18Dec 17, 2013Updated 12 years ago