AngeloJacobo / ULX3S_FPGA_Sobel_Edge_Detection_OV7670Links
Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board
☆16Updated 3 years ago
Alternatives and similar repositories for ULX3S_FPGA_Sobel_Edge_Detection_OV7670
Users that are interested in ULX3S_FPGA_Sobel_Edge_Detection_OV7670 are comparing it to the libraries listed below
Sorting:
- Small (Q)SPI flash memory programmer in Verilog☆63Updated 2 years ago
- Master-thesis-final☆19Updated last year
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆67Updated 3 years ago
- A CIC filter implemented in Verilog☆22Updated 9 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆27Updated 4 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- I2C Master Verilog module☆34Updated 3 weeks ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆90Updated 5 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆82Updated 2 years ago
- Delta Sigma DAC FPGA☆41Updated 4 months ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆16Updated 5 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆17Updated 5 years ago
- Project: Precise Measure of time delays in FPGA☆30Updated 7 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆71Updated 3 years ago
- ULPI Link Wrapper (USB Phy Interface)☆28Updated 5 years ago
- IEEE P1735 decryptor for VHDL☆32Updated 10 years ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Sata 2 Host Controller for FPGA implementation☆17Updated 7 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆36Updated last year
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆51Updated last week
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆79Updated last year
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆23Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- USB 1.1 Host and Function IP core☆23Updated 10 years ago