Alternatives and similar repositories for UVMReference

Users that are interested in UVMReference are comparing it to the libraries listed below

• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆250Updated 12 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆199Updated 4 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆151Updated 5 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆410Updated last year
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆140Updated 2 weeks ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆192Updated 8 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆173Updated 6 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆556Updated 3 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆311Updated 3 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆426Updated 2 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆105Updated 6 months ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆144Updated 7 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆127Updated 4 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆121Updated 7 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆209Updated 2 years ago
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆105Updated 11 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆139Updated 3 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆138Updated 4 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆101Updated 7 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆448Updated 5 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆86Updated 7 months ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆115Updated 11 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆440Updated this week
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆86Updated 8 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆354Updated last year
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆92Updated 2 years ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆74Updated 4 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆252Updated 5 months ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆62Updated 2 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆35Updated last year