emard / flearadio
Digital FM Radio Receiver for FPGA
☆60Updated 9 years ago
Alternatives and similar repositories for flearadio:
Users that are interested in flearadio are comparing it to the libraries listed below
- Collection of projects for various FPGA development boards☆44Updated 10 months ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆61Updated 6 years ago
- ☆45Updated 2 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆92Updated 8 years ago
- USB serial device (CDC-ACM)☆38Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆86Updated 6 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆42Updated 11 months ago
- USB Full Speed PHY☆42Updated 4 years ago
- Small footprint and configurable JESD204B core☆42Updated 2 months ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 3 years ago
- Small (Q)SPI flash memory programmer in Verilog☆61Updated 2 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆42Updated 4 years ago
- i2s core, with support for both transmit and receive☆29Updated 6 years ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- DPLL for phase-locking to 1PPS signal☆31Updated 8 years ago
- Tiny tips for Colorlight i5 FPGA board☆56Updated 4 years ago
- Extensible FPGA control platform☆59Updated last year
- Portable HyperRAM controller☆54Updated 3 months ago
- sliding DFT for FPGA, targetting Lattice ICE40 1k☆73Updated 4 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆50Updated 2 months ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆28Updated 2 years ago
- VHDL Modules☆24Updated 10 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated 10 months ago
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 6 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆53Updated 2 years ago
- Wishbone interconnect utilities☆39Updated last month