JacoboJin / RISCV-on-PYNQ-Z2
This repo is to inplemente the riscv soc on the xilinx pynq-z2 board
☆10Updated 11 months ago
Related projects ⓘ
Alternatives and complementary repositories for RISCV-on-PYNQ-Z2
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- Convolution Neural Network of vgg19 model in verilog☆43Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- This is a verilog implementation of 4x4 systolic array multiplier☆39Updated 4 years ago
- ☆64Updated 2 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆48Updated 7 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model archite…☆34Updated last year
- ☆60Updated 5 years ago
- eyeriss-chisel3☆39Updated 2 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆75Updated this week
- PYNQ Composabe Overlays☆67Updated 5 months ago
- ☆25Updated 4 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- ☆26Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- Hardware implementation of HDR image producing algorithm☆15Updated 2 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆27Updated 3 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- DMA controller for CNN accelerator☆12Updated 7 years ago
- Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional N…☆13Updated 7 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆29Updated 5 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆9Updated last year
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆42Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆31Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆23Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆44Updated 3 years ago