Alternatives and similar repositories for RISCV-on-PYNQ-Z2

Users that are interested in RISCV-on-PYNQ-Z2 are comparing it to the libraries listed below

• yuyuranium / RTOS-Project-2023-riscv-freertos-on-pynq
  Porting FreeRTOS to a RISC-V based system on PYNQ-Z2
  ☆10Updated 5 months ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆31Updated 2 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆38Updated 2 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• obilaniu / MVU
  Neural Network accelerator powered by MVUs and RISC-V.
  ☆13Updated 10 months ago
• kuladeepsaireddy / OpenNoc
  ☆33Updated 6 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆54Updated 4 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆103Updated 4 years ago
• ljgibbslf / basic_cache_core
  ☆28Updated 4 years ago
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆34Updated last year
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆75Updated last year
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆51Updated 4 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆28Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆50Updated last year
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆56Updated this week
• pulp-platform / fpu
  ☆49Updated 6 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆21Updated 3 weeks ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆45Updated 2 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆49Updated 7 years ago
• pulp-platform / ITA
  ☆47Updated last month
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 3 years ago
• Noris4est / I2C-FPGA-Verilog-HDL
  In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…
  ☆17Updated 5 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆47Updated 5 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆44Updated 8 months ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆64Updated 9 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆40Updated 4 years ago
• zhongguanggong / ggz
  使用FPGA实现CNN模型
  ☆15Updated 5 years ago
• mfkiwl / E203_dma
  ☆10Updated 4 years ago