This repo is to inplemente the riscv soc on the xilinx pynq-z2 board
☆12Dec 6, 2023Updated 2 years ago
Alternatives and similar repositories for RISCV-on-PYNQ-Z2
Users that are interested in RISCV-on-PYNQ-Z2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆13Dec 26, 2024Updated last year
- This project presents the implementation of Quantum Key Distribution (QKD) Protocol:BB84 on FPGA. Quantum Communication Methodology has b…☆14Dec 29, 2022Updated 3 years ago
- 黃鐘揚老師的"系統晶片驗證"作業與專題(SoCV)☆11Jan 18, 2024Updated 2 years ago
- 最小和算法实现☆10Jul 12, 2020Updated 6 years ago
- A Vivado IP package of the PicoRV32 RISC-V processor☆16Jul 9, 2020Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- http://os.cs.tsinghua.edu.cn/research/undergraduate/zwpu2019☆12Jun 7, 2019Updated 7 years ago
- ☆19Aug 22, 2022Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆36Aug 21, 2026Updated 3 weeks ago
- 8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving…☆18Jul 21, 2022Updated 4 years ago
- We made ISAC radar using Zedboard and AD9361, by receiving the transmitted chirp signals, calculating the autocorrelation and FFT to get …☆27Jan 11, 2025Updated last year
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 4 years ago
- Declare & parse types / dataclasses / functions based on Python type annotations☆24Jul 29, 2026Updated last month
- OpenTestability is an open-source tool for structural analysis of digital circuits, enabling computation of SCOAP metrics, Controllibilit…☆20Aug 18, 2026Updated last month
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- APB Logic☆29Updated this week
- Petri Net Simulator program☆10Nov 27, 2017Updated 8 years ago
- B站抢票☆25Apr 25, 2024Updated 2 years ago
- UVM Verification Environment for the CVFPU☆24Aug 27, 2026Updated 3 weeks ago
- Flip flop setup, hold & metastability explorer tool☆52Jul 12, 2026Updated 2 months ago
- ☆25Jul 30, 2025Updated last year
- Simodense: a RISC-V softcore for custom SIMD instructions☆17Aug 9, 2026Updated last month
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆27Aug 23, 2021Updated 5 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- Markdown to PPT☆29Mar 16, 2015Updated 11 years ago
- ☆26Apr 3, 2026Updated 5 months ago
- IC-contest 2012~2024☆26Apr 30, 2024Updated 2 years ago
- Modular RISC-V implementation & SoC☆21Aug 29, 2026Updated 2 weeks ago
- Matrix multiplication accelerator on ZYNQ SoC.☆13Apr 29, 2025Updated last year
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 3 years ago
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆45May 12, 2016Updated 10 years ago
- RTL implementation of a ray-tracing GPU☆17Dec 18, 2012Updated 13 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆13May 6, 2026Updated 4 months ago
- Design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit Version 1 in TSMC 16nm☆23Sep 8, 2026Updated last week
- ccsds ldpc encdoer and decoder.(CCSDS 131.1-O-2)☆26Sep 25, 2024Updated last year
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆46Nov 27, 2022Updated 3 years ago
- LSTM neural network (verilog)☆16Dec 5, 2018Updated 7 years ago
- Research enablement kit for designing and prototyping a Cortex-M0–based SoC with custom IP integration (education, research)☆18Jun 13, 2025Updated last year
- RISC-V soft-SoC extensible plaftorm for Xilinx FPGAs from University of Naples Federico II.☆19Sep 10, 2026Updated last week