Alternatives and similar repositories for training

Users that are interested in training are comparing it to the libraries listed below

• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆40Updated 2 years ago
• adamgallas / MIT_Bluespec_RISCV_Tutorial
  ☆22Updated 2 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆162Updated 7 months ago
• cry-daniel / Computer-Architecture-Learning
  ☆61Updated 2 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 9 months ago
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆17Updated 6 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆136Updated 11 months ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆63Updated last year
• yuhanzhu612 / OSCPU
  我的一生一芯项目
  ☆16Updated 3 years ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 2 months ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆48Updated last year
• OpenXiangShan / GEM5
  ☆86Updated this week
• Ch-EnShen / UCB-CS152-all-materials
  This repository collects all materials from past years of cs152.
  ☆47Updated 10 months ago
• Shuiliusheng / boom_stop
  jump to a place when progam runs to the max instruction number
  ☆11Updated last year
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆28Updated 5 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• JamesAslan / MicroArchBench
  ☆72Updated 7 months ago
• OSCPU / yosys-sta
  ☆64Updated last month
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆51Updated 3 years ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆36Updated 3 years ago
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆30Updated 2 years ago
• USTC-System-Courses / CECS-Lab
  ☆38Updated last year
• yyNoBug / RISCV-CPU
  A FPGA-supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL. Achieve good performance due to optimizations like branch p…
  ☆9Updated 5 years ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆35Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆38Updated 2 years ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• brochz / riscv_151
  An implementation of RV32I based on EECS151
  ☆8Updated last year