athurg / cadenceLinks
Cadence PCB and SCH Library and some tools
☆14Updated 10 years ago
Alternatives and similar repositories for cadence
Users that are interested in cadence are comparing it to the libraries listed below
Sorting:
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆25Updated 3 years ago
- 4-Layer XC7Z010 DDR3 Layout☆18Updated 3 years ago
- ☆18Updated 5 years ago
- 基于Kintex-7 XC7K325T的高性能FPGA功能验证板☆18Updated 5 years ago
- A collection of Opal Kelly provided design resources☆17Updated this week
- This is BISS-C FPGA IP and It's Driver Repo☆32Updated last year
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取…☆28Updated 10 years ago
- KiCad PCB project of Logic Analyzer☆43Updated 4 years ago
- ☆21Updated 10 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Updated 7 years ago
- Communication channel from FPGA (Alterra EP4CE10) and Linux (Lichee PI Allwinner V3S)☆28Updated 5 years ago
- Verilog modules for software-defined radio.☆18Updated 12 years ago
- My self-designed ZYNQ-7010 4-layer developement board.☆32Updated 4 years ago
- Vivado project for the SP701 Imaging application project☆13Updated 5 years ago
- USB serial device (CDC-ACM)☆41Updated 5 years ago
- FPGA core boards / evaluation boards based on CDCTL hardware☆93Updated 4 years ago
- USB capture IP☆22Updated 5 years ago
- Time to Digital Converter (TDC)☆34Updated 4 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆29Updated 8 years ago
- Open source zynq platform☆18Updated 7 years ago
- general-cores☆21Updated 3 months ago
- MMC (and derivative standards) host controller☆24Updated 5 years ago
- Imaging application using MIPI and DisplayPort to process image☆25Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆28Updated 4 years ago