Cadence PCB and SCH Library and some tools
☆14Jan 9, 2015Updated 11 years ago
Alternatives and similar repositories for cadence
Users that are interested in cadence are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Jupyter kernel for Cadence SKILL☆22Feb 16, 2017Updated 9 years ago
- Cadence Allegro Skills.☆61Jul 10, 2019Updated 7 years ago
- stm32控制伺服电机☆15Jul 26, 2022Updated 4 years ago
- GUI that provides functionality making Cadence PCBs Layout much easier to read and review, written in the Skill variant of Lisp.☆15Feb 16, 2022Updated 4 years ago
- This repository contains embedded hardware designs auto-created from Circuit Tree web application by random requirements generated from p…☆30Oct 16, 2018Updated 8 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Utilities for working with Cadence's SKILL/SKILL++ including a unit testing framework.☆49Nov 6, 2020Updated 6 years ago
- cadence-cis-allegro-library☆17May 16, 2013Updated 13 years ago
- 基于ucos的模块化开发框架☆10Aug 30, 2019Updated 7 years ago
- Open Source Layouts, Footprints, Schematics, Libraries, ... for Cadence Products☆12Sep 13, 2022Updated 4 years ago
- ORPSoC fork (from git://openrisc.net/stefan/orpsoc) for de0_nano board with custom made expansion board☆12Sep 26, 2013Updated 13 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- Real Digital Vivado IP Library☆10Nov 13, 2022Updated 3 years ago
- Library for reading Xilinx .bit bitstream file headers with metadata extraction☆14Apr 7, 2026Updated 6 months ago
- A programming language for FPGAs.☆19May 5, 2018Updated 8 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- a collection of open sourced VHDL for cryptography☆12Aug 10, 2018Updated 8 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 7 months ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆21Nov 13, 2024Updated last year
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- Multi-function, universal, fixed-point CORDIC☆16Feb 20, 2022Updated 4 years ago
- Inter Process Communication (IPC) between Python and Cadence Virtuoso☆83Dec 22, 2016Updated 9 years ago
- A Cadence Allegro PCB schematics parser and verification tool. Together with IBERTpy can configure, run, and compile Vivado IBERT eye dia…☆13Apr 17, 2021Updated 5 years ago
- TSMC_MPC_PMSM:foc☆15Sep 28, 2018Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An Inexpensive Vector Network Analyzer Project for the Walla Walla University Electronics II Class☆12Jun 10, 2019Updated 7 years ago
- build mainline SBI and Linux for allwinner D1 nezha board☆11Jun 30, 2021Updated 5 years ago
- USB monitor Linux kernel driver.☆11Jan 8, 2025Updated last year
- Audio Signal Processing SoC☆20Mar 13, 2018Updated 8 years ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated 2 years ago
- serT 远程串口透传模块, 部分开源, 开源部分遵守MIT协议☆12Feb 9, 2017Updated 9 years ago
- 磁场矢量控制云台电机程序,使用MT6813获取位置角度,使用uart串口实现modbus RTU通讯 ,电流环16K,速度环8K,位置环4K,STM32F103C8T6主控,开发环境keil☆12Sep 10, 2024Updated 2 years ago
- VHDL Native Synthesizable Library☆14Oct 27, 2026Updated last week
- 【无刷电机FOC驱动器】双通道 FOC 无刷电机驱动套件,最高电压 60V 单通道电流可达 100A,可以驱动 1.2kW 以内 BLDC 或 PMSM(有中文注释)。☆22Feb 6, 2026Updated 9 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Cadence Skilll support for Sublime Text☆18Feb 23, 2017Updated 9 years ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆13Jan 26, 2026Updated 9 months ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆21Feb 27, 2024Updated 2 years ago
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- The FPGA design for the FreeSRP's Artix 7 FPGA☆25Apr 12, 2017Updated 9 years ago
- ☆17Oct 6, 2023Updated 3 years ago
- core files for the MiST fpga☆33Nov 22, 2024Updated last year