athurg / cadenceLinks
Cadence PCB and SCH Library and some tools
☆13Updated 10 years ago
Alternatives and similar repositories for cadence
Users that are interested in cadence are comparing it to the libraries listed below
Sorting:
- Open source zynq platform☆18Updated 7 years ago
- 4-Layer XC7Z010 DDR3 Layout☆17Updated 3 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆24Updated 3 years ago
- Adapter board exposing SATA M.2 SSD on FMC board-to-board connector☆12Updated last year
- KiCad PCB project of Logic Analyzer☆42Updated 4 years ago
- Absolute encoder VHDL core☆20Updated 8 years ago
- Open Source Layouts, Footprints, Schematics, Libraries, ... for Cadence Products☆12Updated 2 years ago
- FT2232HL JTAG & UART Downloader☆17Updated 3 years ago
- This is a C library to interface with the LiteX Firmware on Thunderscope over PCIe☆11Updated this week
- This is BISS-C FPGA IP and It's Driver Repo☆28Updated last year
- Testbenches for HDL projects☆18Updated last week
- FTDI EEPROM User Area Writer For Xilinx JTAG Programmer☆12Updated 11 years ago
- GUI that provides functionality making Cadence PCBs Layout much easier to read and review, written in the Skill variant of Lisp.☆9Updated 3 years ago
- 基于Kintex-7 XC7K325T的高性能FPGA功能验证板☆19Updated 5 years ago
- ☆28Updated 4 years ago
- Yet Another XC7Z010 Board☆17Updated 3 years ago
- PulseRain FP51 MCU, with peripherals☆15Updated 7 years ago
- Communication channel from FPGA (Alterra EP4CE10) and Linux (Lichee PI Allwinner V3S)☆29Updated 5 years ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取…☆27Updated 9 years ago
- an sata controller using smallest resource.☆16Updated 11 years ago
- SpaceVNX (VITA 74.4) carrier based on Zynq-7000.☆13Updated 2 years ago
- OpenFPGA ICE40UP5K☆33Updated 4 years ago
- The program for USB-Blaster Chinese version on STM32 works with☆31Updated 7 years ago
- ☆48Updated 4 years ago
- Altium PCB project for the Titan PCI Express development card. This card uses the Lattice ECP5 FPGA.☆19Updated 10 years ago
- SEA-S7_gesture recognition☆16Updated 4 years ago
- OscillatorIMP ecosystem FPGA IP sources☆28Updated last week
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆29Updated 8 years ago
- Simple mono FM Radio.☆48Updated 9 years ago
- Time to Digital Converter (TDC)☆30Updated 4 years ago