FPL'26 Optimization Contest
☆55Sep 15, 2026Updated last month
Alternatives and similar repositories for fpl26_optimization_contest
Users that are interested in fpl26_optimization_contest are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆18May 25, 2026Updated 5 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆37Jun 3, 2025Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆102Apr 30, 2025Updated last year
- Pathfinder routing algorithm practice☆16May 2, 2017Updated 9 years ago
- Build Customized FPGA Implementations for Vivado☆395Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- AI-assisted FPGA development across AMD Vivado, Anlogic TangDynasty, and Intel Quartus.☆56Aug 17, 2026Updated 2 months ago
- 24bit CPU with integrated GPU made in Logisim☆15Mar 3, 2026Updated 7 months ago
- MCP server that holds vivado and allows access to vivado without starting a new batch command every time☆67Feb 19, 2026Updated 8 months ago
- ☆19Jul 2, 2024Updated 2 years ago
- ☆16May 23, 2024Updated 2 years ago
- ☆15Jul 19, 2024Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆18Oct 22, 2026Updated last week
- ☆55Dec 10, 2024Updated last year
- ☆21Sep 15, 2024Updated 2 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆21Jul 9, 2024Updated 2 years ago
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆21Jan 21, 2022Updated 4 years ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆179Updated this week
- Tools for FPGA Assurance Flows☆14Sep 25, 2026Updated last month
- ☆32Oct 12, 2023Updated 3 years ago
- Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring☆20Sep 28, 2026Updated last month
- ISPD26 Contest: Post-Placement Buffering and Sizing☆35May 3, 2026Updated 5 months ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆41Aug 13, 2024Updated 2 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆42Sep 19, 2026Updated last month
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆76Jul 1, 2026Updated 3 months ago
- A variant of Tinyhttpd.☆12Jan 30, 2026Updated 8 months ago
- discrete gate sizing☆14Nov 23, 2020Updated 5 years ago
- 3D FPGA Architecture Exploration Tool☆28Jun 22, 2026Updated 4 months ago
- ☆221Updated this week
- ☆64Jul 4, 2022Updated 4 years ago
- HW-GPT-Bench: Hardware-Aware Architecture Benchmark for Language Models☆25Dec 6, 2024Updated last year
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆116Mar 9, 2024Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 基于FPGA-Pynq的车牌识别系统。The LPR system of FPGA-Pynq☆13Mar 22, 2019Updated 7 years ago
- Official implementation of DAC'26 paper "FlowPlace: Flow Matching for Chip Placement"☆17May 15, 2026Updated 5 months ago
- An agent skill that turns an HDL / RTL / SoC architecture description into a clean SVG block diagram☆28Aug 10, 2026Updated 2 months ago
- ☆23May 12, 2026Updated 5 months ago
- Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…☆23Nov 18, 2025Updated 11 months ago
- ☆15Jun 24, 2025Updated last year
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago