Inference Engine for SiliconMind-V1 Verilog Coding Models
☆53Jun 2, 2026Updated 4 months ago
Alternatives and similar repositories for SiliconMind-V1
Users that are interested in SiliconMind-V1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A desktop VRM character (小光) that gives your AI agent a face — chats, speaks, listens, lip-syncs, and emotes on macOS.☆28Jul 19, 2026Updated 3 months ago
- 簡韶逸老師的"電腦視覺"作業與專題(CV)☆24Jan 18, 2024Updated 2 years ago
- AI-Powered Hardware Design & Verification Copilot - Plugin for your CLI☆23Jul 12, 2026Updated 3 months ago
- ☆12Apr 7, 2021Updated 5 years ago
- TAIDL: Tensor Accelerator ISA Definition Language☆25Updated this week
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- The shortest path from PyTorch to custom ASICs.☆112Sep 26, 2026Updated 3 weeks ago
- OpenROAD's Chatbot Assistant☆48Oct 15, 2026Updated last week
- a collection of CUDA Kernels☆18Jul 24, 2026Updated 2 months ago
- ☆40Sep 17, 2024Updated 2 years ago
- [NeurIPS 2026] Veri-Sure: Multi-Agent RTL Code Generation with Temporal Tracing, Slicing and Formal Verification☆28Oct 15, 2026Updated last week
- ☆15Jun 24, 2025Updated last year
- ISEDA'26 LEGO official Repo☆30Apr 8, 2026Updated 6 months ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆142Apr 11, 2025Updated last year
- A Rocket-Chip with a Dynamically Randomized LLC☆13Sep 18, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Professor: C.H. Yang☆11Oct 6, 2026Updated 2 weeks ago
- I independently completed all five labs and wrote additional notes for Labs 1, 2, 3, and 5.☆27Oct 14, 2025Updated last year
- LintLLM is an open-source Verilog linting framework powered by Large Language Models (LLMs).☆12Aug 14, 2026Updated 2 months ago
- ☆14Jan 4, 2023Updated 3 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- ☆31Aug 18, 2025Updated last year
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆25Apr 25, 2025Updated last year
- ☆17Jan 25, 2021Updated 5 years ago
- ☆29Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆50Feb 27, 2024Updated 2 years ago
- [COLM25] Enhancing Autoformalization with no Labeled Data☆14Aug 26, 2025Updated last year
- A tiny Verilog CNN accelerator for the Tang Nano 20K. Features INT8 quantized weights, a streaming MAC array, and full on-chip MNIST infe…☆17May 26, 2026Updated 4 months ago
- The Atlas multi-GPU quantum circuit simulator.☆15Aug 17, 2024Updated 2 years ago
- 《Reinforcement Learning from Human Feedback》繁體中文全譯本+每章互動實驗 | Unofficial zh-TW community translation of the RLHF Book with interactive lab…☆179Jul 10, 2026Updated 3 months ago
- A 4x4 Weight Stationary Systolic Array Implementation☆15Oct 16, 2023Updated 3 years ago
- My Configs and Dotfiles 🫥☆18Updated this week
- 丁建均老師的"時頻分析和小波轉換"作業(TFW)☆14Jan 18, 2024Updated 2 years ago
- [ICLR'25 Spotlight] Rethinking and improving autoformalization: towards a faithful metric and a Dependency Retrieval-based approach☆30May 20, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆34Feb 24, 2026Updated 7 months ago
- 不定期更新☆150Sep 28, 2026Updated 3 weeks ago
- A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.☆16Aug 7, 2022Updated 4 years ago
- To take down the code that I've written in course.☆12Jun 23, 2024Updated 2 years ago
- ☆15Feb 2, 2026Updated 8 months ago
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆34May 4, 2025Updated last year
- Safe high-level bindings for the Boolector SMT solver☆14Apr 5, 2022Updated 4 years ago