Xilinx / SDx

Related projects: ⓘ

• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆54Updated 7 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 4 years ago
• warclab / dyract
  DyRACT Open Source Repository
  ☆16Updated 8 years ago
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆39Updated 5 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆44Updated 4 years ago
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 2 years ago
• LEAP-FPGA / leap-documentation
  ☆24Updated 8 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 7 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 2 months ago
• socrocket / core
  SoCRocket - Core Repository
  ☆32Updated 7 years ago
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆30Updated last year
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 2 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆161Updated 11 months ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆53Updated 3 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• pretis / flexpret
  ☆55Updated this week
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆86Updated 3 months ago
• secworks / siphash
  Hardware implementation of the SipHash short-inout PRF
  ☆17Updated 3 years ago
• Xilinx / bootgen
  bootgen source code
  ☆33Updated last month
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• sangwoojun / bluespecpcie
  PCIe library for the Xilinx 7 series FPGAs in the Bluespec language
  ☆69Updated 2 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆118Updated 10 years ago
• maltevesper / JetStream-hardware
  ☆22Updated 8 years ago
• esperantotech / boom-template
  A template for building new projects/platforms using the BOOM core.
  ☆24Updated 5 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 4 years ago
• yansyaf / cmake-verilog-vhdl-fpga-template
  CMake template for Verilog and VHDL project and Altera/Xilinx FPGA target
  ☆20Updated last year
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆68Updated 4 years ago
• ripopov / gdb_systemc_trace
  gdb python scripts for SystemC design introspection and tracing
  ☆29Updated 5 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆65Updated 4 years ago