Alternatives and similar repositories for fpga-partial-reconfig

Users that are interested in fpga-partial-reconfig are comparing it to the libraries listed below

• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 3 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆48Updated 9 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆37Updated 8 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆199Updated 7 months ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆37Updated 8 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆138Updated last week
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆83Updated 3 weeks ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆82Updated 5 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• idea-fasoc / fasoc
  ☆54Updated last year
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆65Updated 3 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆57Updated 5 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆55Updated 2 years ago
• sveditor / sveditor
  SystemVerilog Development Environment
  ☆53Updated 3 years ago
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆59Updated 2 months ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 6 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆59Updated 3 years ago
• cjdrake / AES
  Advanced Encryption Standard (AES) SystemVerilog Core
  ☆34Updated 7 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆135Updated this week
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆170Updated last year