Alternatives and similar repositories for PoC

Users that are interested in PoC are comparing it to the libraries listed below

• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆78Updated last week
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆34Updated 2 weeks ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 10 months ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 5 months ago
• VHDL / news
  VHDL related news.
  ☆27Updated last week
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆48Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated last week
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆59Updated last month
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆70Updated 2 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆26Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 5 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆50Updated 3 years ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆26Updated last year
• VUnit / vunit_action
  VUnit GitHub action
  ☆19Updated 4 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• TerosTechnology / teroshdl-documenter-demo
  This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…
  ☆10Updated 3 years ago
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated 2 years ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆72Updated this week
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 9 years ago
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated 10 months ago
• LarsAsplund / github-facts
  GitHub-based statistics highlighting interesting facts about the HDL industry
  ☆12Updated 2 years ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 7 months ago
• edaa-org / pyEDAA.UCIS
  Unified Coverage Interoperability Standard (UCIS)
  ☆13Updated 3 weeks ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆73Updated 2 weeks ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆45Updated this week
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆42Updated 3 months ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆69Updated 2 months ago