Alternatives and similar repositories for PoC:

Users that are interested in PoC are comparing it to the libraries listed below

• TerosTechnology / teroshdl-documenter-demo
  This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…
  ☆10Updated 3 years ago
• VHDL / news
  VHDL related news.
  ☆25Updated this week
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 4 years ago
• LarsAsplund / github-facts
  GitHub-based statistics highlighting interesting facts about the HDL industry
  ☆12Updated last year
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆12Updated 2 months ago
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated this week
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated last year
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆23Updated 5 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 2 years ago
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆30Updated 2 months ago
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆14Updated 3 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last month
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated 3 months ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆14Updated 5 years ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated 11 months ago
• NJDFan / register-maps
  Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.
  ☆12Updated 2 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆12Updated last year
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated 2 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆29Updated 2 weeks ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆15Updated 8 years ago
• schang412 / cocotbext-spi
  ☆21Updated last week
• pulp-platform / svase
  ☆31Updated 3 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆60Updated this week
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆23Updated 9 months ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆41Updated 2 years ago