Alternatives and similar repositories for PoC

Users that are interested in PoC are comparing it to the libraries listed below

• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆55Updated 3 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated 2 weeks ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 8 months ago
• VHDL / news
  VHDL related news.
  ☆26Updated this week
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆47Updated last year
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆27Updated 2 months ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• TerosTechnology / teroshdl-documenter-demo
  This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…
  ☆10Updated 3 years ago
• LarsAsplund / github-facts
  GitHub-based statistics highlighting interesting facts about the HDL industry
  ☆12Updated 2 years ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆55Updated 2 months ago
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated 2 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 5 months ago
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated 8 months ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆46Updated 3 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆50Updated this week
• schang412 / cocotbext-spi
  ☆25Updated 5 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated this week
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆62Updated 4 years ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆15Updated 5 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 2 months ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆67Updated this week
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆80Updated 3 years ago
• VHDL / CoreLib
  A VHDL Core Library.
  ☆17Updated 8 years ago
• edaa-org / pyEDAA.UCIS
  Unified Coverage Interoperability Standard (UCIS)
  ☆12Updated 4 months ago
• wallento / cocotbext-uart
  UART cocotb module
  ☆11Updated 4 years ago