SoCFPGA-learning / Chameleon96Links
The Chameleon96™ board, based on Intel® Cyclone V SoC FPGA
☆15Updated last year
Alternatives and similar repositories for Chameleon96
Users that are interested in Chameleon96 are comparing it to the libraries listed below
Sorting:
- Miscellaneous ULX3S examples (advanced)☆78Updated last week
- An FPGA/PCI Device Reference Platform☆28Updated 4 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 3 years ago
- Cyclone V bitstream reverse-engineering project☆124Updated last year
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆12Updated 2 years ago
- DVI video out example for prjtrellis☆16Updated 6 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆37Updated 2 years ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆32Updated 8 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆17Updated 3 years ago
- ☆12Updated last week
- 5-stage RISC-V CPU, originally developed for RISCBoy☆27Updated last year
- A port of the OPL3 to the Panologic G1 thin client☆20Updated 5 years ago
- A simple 6502 system built on a Lattice Ultra Plus 5k FPGA☆12Updated 6 years ago
- Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs☆31Updated 3 years ago
- sn76489an compatible Verilog core, with emphasis on FPGA implementation and Megadrive/Master System compatibility☆31Updated 5 months ago
- ☆50Updated 2 years ago
- A repository for a random collection of stuff pertaining to reverse engineering the Pano Logic G2 "zero" client☆34Updated 6 years ago
- Documenting the Microchip (Atmel) ATF15xx CPLD fuse maps and programming algorithms☆57Updated 2 weeks ago
- Quartus Lite docker☆39Updated 4 years ago
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆44Updated 5 months ago
- Reusable Verilog 2005 components for FPGA designs☆44Updated 4 months ago
- Collection of PMOD boards for the use with iCEBreaker and any other FPGA board that has PMOD connectors.☆91Updated last year
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- Open source hardware down to the chip level!☆30Updated 3 years ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- USB DFU bootloader gateware / firmware for FPGAs☆65Updated 8 months ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- simple commandline jtag stuff☆33Updated 7 years ago
- understanding the tinyfpga bootloader☆24Updated 7 years ago