Slides of Dr Sparsh Mittal on "Computer Architecture for AI" (aka Hardware Architecture for Deep Learning) Course
☆19Apr 20, 2026Updated 4 months ago
Alternatives and similar repositories for ComputerArchitectureForAI_Slides_DrSparshMittal
Users that are interested in ComputerArchitectureForAI_Slides_DrSparshMittal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Dr Sparsh's lecture slides on RISC-V ISA☆22Jun 9, 2025Updated last year
- ☆11May 30, 2024Updated 2 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆26Dec 21, 2025Updated 8 months ago
- Filter builder tool☆18Apr 11, 2022Updated 4 years ago
- YosysHQ SVA AXI Properties☆56Feb 7, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SPICE Station AI — releases☆41Aug 6, 2026Updated last month
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Mar 30, 2025Updated last year
- SystemVerilog modules and classes commonly used for verification☆58Jan 5, 2026Updated 8 months ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆14Jan 5, 2018Updated 8 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆16Jan 14, 2021Updated 5 years ago
- Building a Computer From Scratch with verilog☆11Feb 6, 2026Updated 7 months ago
- Verilog Fundamentals Explained for Beginners and Professionals☆20Jan 15, 2023Updated 3 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 2 years ago
- Practices related to the fundamental level of the programming language Verilog.☆13Jan 16, 2023Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆17Aug 26, 2021Updated 5 years ago
- RISC-V Nox core☆72Jul 22, 2025Updated last year
- General Purpose AXI Direct Memory Access☆80May 12, 2024Updated 2 years ago
- Pequeno R5 (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32IM ISA.☆158Aug 21, 2026Updated 3 weeks ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆52Jul 11, 2025Updated last year
- Dual-core 16-bit RISC processor☆12Jul 21, 2024Updated 2 years ago
- Course material for Purdue ECE57000 Artificial Intelligence☆16Nov 8, 2018Updated 7 years ago
- The course contest involves a multi-player capture-the-flag variant of Pacman, where agents control both Pacman and ghosts in coordinated…☆12Jan 24, 2021Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆91May 2, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆17Aug 21, 2018Updated 8 years ago
- Software-based rasterization library☆11Jan 30, 2023Updated 3 years ago
- A game of life🔬 simulator on an infinite♾️ plane☆16Oct 15, 2021Updated 4 years ago
- Part of paper: Massively Parallel Combinational Binary Neural Networks for Edge Processing☆12Jun 27, 2019Updated 7 years ago
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- A place to keep my synthesizable verilog examples.☆59May 19, 2026Updated 4 months ago
- A complete UVM TB for verification of single port 64KB RAM☆18Apr 16, 2021Updated 5 years ago
- This repository consists of all chipdev.io practice questions☆32Oct 11, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆17Updated this week
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆15Aug 26, 2024Updated 2 years ago
- Perceptron-based branch predictor written in C++☆14Dec 14, 2016Updated 9 years ago
- miniSpartan6+ (Spartan6) FPGA based MP3 Player☆28Sep 2, 2019Updated 7 years ago
- Modular Graphical Simulator for Teaching Microprogramming☆13Dec 16, 2024Updated last year
- PCB design for the initial prototype of OBC hardware, to interface with LaunchPad.☆10Sep 19, 2018Updated 8 years ago
- Advanced STM32H7 autopilot☆10Apr 13, 2023Updated 3 years ago