Slides of Dr Sparsh Mittal on "Computer Architecture for AI" (aka Hardware Architecture for Deep Learning) Course
☆18Apr 20, 2026Updated 3 months ago
Alternatives and similar repositories for ComputerArchitectureForAI_Slides_DrSparshMittal
Users that are interested in ComputerArchitectureForAI_Slides_DrSparshMittal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Dr Sparsh's lecture slides on RISC-V ISA☆22Jun 9, 2025Updated last year
- ☆11May 30, 2024Updated 2 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated 7 months ago
- Filter builder tool☆18Apr 11, 2022Updated 4 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆22Jul 28, 2026Updated last week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 13 years ago
- YosysHQ SVA AXI Properties☆53Feb 7, 2023Updated 3 years ago
- SPICE Station AI — releases☆42Updated this week
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆19Mar 30, 2025Updated last year
- ☆16Mar 27, 2024Updated 2 years ago
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 7 months ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆14Jan 5, 2018Updated 8 years ago
- Building a Computer From Scratch with verilog☆11Feb 6, 2026Updated 6 months ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated 10 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 2 years ago
- Practices related to the fundamental level of the programming language Verilog.☆13Jan 16, 2023Updated 3 years ago
- RISC-V Nox core☆72Jul 22, 2025Updated last year
- General Purpose AXI Direct Memory Access☆78May 12, 2024Updated 2 years ago
- This repository includes codes created for a graduate level Perception course at the University of Maryland. The repo includes codes for …☆17Oct 24, 2017Updated 8 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆155Oct 2, 2025Updated 10 months ago
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆50Jul 11, 2025Updated last year
- Dual-core 16-bit RISC processor☆12Jul 21, 2024Updated 2 years ago
- 👻 Simple Undertale-like game on Basys3 FPGA written in Verilog☆16Jul 3, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- The course contest involves a multi-player capture-the-flag variant of Pacman, where agents control both Pacman and ghosts in coordinated…☆12Jan 24, 2021Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆87May 2, 2021Updated 5 years ago
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆17Aug 21, 2018Updated 7 years ago
- Software-based rasterization library☆11Jan 30, 2023Updated 3 years ago
- A game of life🔬 simulator on an infinite♾️ plane☆16Oct 15, 2021Updated 4 years ago
- An inhouse RISC-V 32-bits CPU☆20Feb 12, 2026Updated 5 months ago
- Part of paper: Massively Parallel Combinational Binary Neural Networks for Edge Processing☆12Jun 27, 2019Updated 7 years ago
- UART cocotb module☆11Jun 30, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- A place to keep my synthesizable verilog examples.☆58May 19, 2026Updated 2 months ago
- A complete UVM TB for verification of single port 64KB RAM☆18Apr 16, 2021Updated 5 years ago
- This repository consists of all chipdev.io practice questions☆28Oct 11, 2023Updated 2 years ago
- Eagle PCB designs for adapting SMD parts to ugly (or Manhattan) style breadboarding☆14Jul 22, 2016Updated 10 years ago
- ☆17Jul 21, 2026Updated 2 weeks ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆13Aug 26, 2024Updated last year