SeoLabCornell / torch2chip
Torch2Chip (MLSys, 2024)
☆51Updated last month
Alternatives and similar repositories for torch2chip:
Users that are interested in torch2chip are comparing it to the libraries listed below
- ☆52Updated this week
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆83Updated 6 months ago
- ☆21Updated 2 months ago
- ☆32Updated 4 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆36Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆48Updated this week
- ☆43Updated 3 years ago
- Implementation of Microscaling data formats in SystemVerilog.☆14Updated 6 months ago
- ☆22Updated this week
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆48Updated last week
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆28Updated 9 months ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆123Updated last year
- ☆39Updated 8 months ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆23Updated 2 years ago
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆32Updated this week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated 3 weeks ago
- Tender: Accelerating Large Language Models via Tensor Decompostion and Runtime Requantization (ISCA'24)☆13Updated 8 months ago
- A survey on Hardware Accelerated LLMs☆49Updated 2 months ago
- ☆39Updated 5 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆25Updated last year
- Official implementation of EMNLP'23 paper "Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference?"☆19Updated last year
- Open-source artifacts and codes of our MICRO'23 paper titled “Sparse-DySta: Sparsity-Aware Dynamic and Static Scheduling for Sparse Multi…☆35Updated last year
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago
- ☆91Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 7 months ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆15Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆42Updated 2 years ago
- Adaptive floating-point based numerical format for resilient deep learning☆14Updated 2 years ago