RobRoyce / fpga_mouse_controller_basys3
USB-to-PS2 mouse controller for FPGAs written in Verilog. Performs clock division, signal sampling, processing, error checking, and validation. Includes Xilinx Basys 3 target configuration.
☆14Updated 3 years ago
Alternatives and similar repositories for fpga_mouse_controller_basys3
Users that are interested in fpga_mouse_controller_basys3 are comparing it to the libraries listed below
Sorting:
- 6-stage in-order dual-issue superscalar risc-v cpu with floating point unit☆12Updated this week
- WISHBONE Interconnect☆11Updated 7 years ago
- Generic AXI master stub☆19Updated 10 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆19Updated 5 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 4 months ago
- Approximate arithmetic circuits for FPGAs☆11Updated 5 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆54Updated 9 months ago
- ☆27Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- fpga verilog risc-v rv32i cpu☆11Updated 2 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- APB Logic☆18Updated 5 months ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 2 years ago
- Switched SRAM-based Multi-ported RAM☆16Updated 6 months ago
- A library of verilog and vhdl modules☆15Updated 6 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆17Updated this week
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆15Updated 3 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆21Updated last year
- Implementation of a cache memory in verilog☆14Updated 7 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- Design and UVM-TB of RISC -V Microprocessor☆18Updated 10 months ago
- A Verilog implementation of a processor cache.☆25Updated 7 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆55Updated 10 months ago
- NoC based MPSoC☆10Updated 10 years ago
- ☆16Updated 6 years ago