RobRoyce / fpga_mouse_controller_basys3Links
USB-to-PS2 mouse controller for FPGAs written in Verilog. Performs clock division, signal sampling, processing, error checking, and validation. Includes Xilinx Basys 3 target configuration.
☆16Updated 3 years ago
Alternatives and similar repositories for fpga_mouse_controller_basys3
Users that are interested in fpga_mouse_controller_basys3 are comparing it to the libraries listed below
Sorting:
- 6-stage in-order dual-issue superscalar risc-v cpu with floating point unit☆14Updated 3 weeks ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆14Updated 13 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆15Updated 3 years ago
- A library of verilog and vhdl modules☆15Updated 6 years ago
- Python script for generating Xilinx .coe files for RAM initializing☆17Updated 6 years ago
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆14Updated 3 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 7 years ago
- The template for VLSI project☆21Updated 6 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- ☆17Updated 5 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆31Updated 4 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆32Updated 9 months ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆21Updated 2 years ago
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- WISHBONE Interconnect☆11Updated 8 years ago
- Generic AXI master stub☆19Updated 11 years ago
- Sata 2 Host Controller for FPGA implementation☆18Updated 7 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆31Updated 3 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆29Updated last year
- Verilog HDL implementation of SDRAM controller and SDRAM model☆30Updated last year
- ☆19Updated 11 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12Updated 6 years ago
- ☆31Updated 3 years ago
- ☆29Updated 2 weeks ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- The Repository contains the code of various Digital Circuits☆11Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago