RobRoyce / fpga_mouse_controller_basys3Links
USB-to-PS2 mouse controller for FPGAs written in Verilog. Performs clock division, signal sampling, processing, error checking, and validation. Includes Xilinx Basys 3 target configuration.
☆16Updated 3 years ago
Alternatives and similar repositories for fpga_mouse_controller_basys3
Users that are interested in fpga_mouse_controller_basys3 are comparing it to the libraries listed below
Sorting:
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆14Updated 13 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆15Updated 3 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆14Updated 3 years ago
- 6-stage in-order dual-issue superscalar risc-v cpu with floating point unit☆14Updated last month
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- A library of verilog and vhdl modules☆15Updated 6 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12Updated 6 years ago
- The Repository contains the code of various Digital Circuits☆11Updated 2 years ago
- Generic AXI master stub☆19Updated 11 years ago
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 7 years ago
- Sata 2 Host Controller for FPGA implementation☆18Updated 7 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆20Updated 2 years ago
- ☆11Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 5 years ago
- ☆30Updated 2 weeks ago
- The template for VLSI project☆21Updated 6 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Updated last year
- IEEE 754 single precision floating point library in systemverilog and vhdl☆32Updated 8 months ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆10Updated 3 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆31Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆29Updated 3 years ago
- A Y86-64 processor implemented using Verilog☆18Updated 4 years ago
- ☆16Updated 5 years ago
- A Verilog implementation of a processor cache.☆28Updated 7 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago