Alternatives and similar repositories for fpga_mouse_controller_basys3

Users that are interested in fpga_mouse_controller_basys3 are comparing it to the libraries listed below

• nhandyal / Verilog-Spectrum-Analyzer
  FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.
  ☆14Updated 13 years ago
• taneroksuz / rv-diios
  6-stage dual-issue in-order superscalar risc-v cpu with floating point unit
  ☆14Updated last month
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆18Updated 4 years ago
• kooltzh / xilinx-coe-generator
  Python script for generating Xilinx .coe files for RAM initializing
  ☆18Updated 6 years ago
• www-asics-ws / wb_conmax
  WISHBONE Interconnect
  ☆11Updated 8 years ago
• abdelazeem201 / SoC-Implementation-of-OpenMSP430-Microcontroller
  The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…
  ☆16Updated 3 years ago
• maazm007 / 100Daysof_RTL
  The Repository contains the code of various Digital Circuits
  ☆11Updated 2 years ago
• chiselverify / vhdl2verilog
  ☆17Updated 5 years ago
• ehw-fit / approx-fpgas
  Approximate arithmetic circuits for FPGAs
  ☆11Updated 5 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆23Updated last year
• dominiksalvet / risc63
  Custom 64-bit pipelined RISC processor
  ☆18Updated last year
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆35Updated last year
• r09g / iadc
  12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm
  ☆22Updated 2 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• abdelazeem201 / ASIC-Implementation-UART
  This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…
  ☆14Updated 3 years ago
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆18Updated 8 years ago
• wnew / hdl_library
  A library of verilog and vhdl modules
  ☆15Updated 7 years ago
• adithyasunil26 / Y86-64-Processor
  A Y86-64 processor implemented using Verilog
  ☆16Updated 4 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆33Updated 4 years ago
• zhujingyang520 / vlsi_project
  The template for VLSI project
  ☆22Updated 6 years ago
• mcrl / NVMe
  ☆35Updated last year
• PacoReinaCampo / MPSoC-RISCV
  Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆13Updated 2 weeks ago
• dpretet / bster
  Implementation of a binary search tree algorithm in a FPGA/ASIC IP
  ☆20Updated 4 years ago
• wjoeyzhewei / Alpha64_R10000_Superscalar_Processor
  Alpha64 R10000 Two-Way Superscalar Processor
  ☆11Updated 6 years ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 8 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆22Updated 2 weeks ago
• EECS150 / fpga_labs_fa21
  FPGA Labs for EECS 151/251A (Fall 2021)
  ☆10Updated 4 years ago
• pulp-platform / apb
  APB Logic
  ☆22Updated 2 weeks ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆32Updated 7 years ago