PranavGovekar / tdcOnFPGA
Implementation of tappped delay line TDC on FPGA
☆12Updated last year
Related projects ⓘ
Alternatives and complementary repositories for tdcOnFPGA
- kintex7 ov13850 fpga mipi camera☆17Updated 9 months ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆45Updated 2 years ago
- A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.☆19Updated 7 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆50Updated 3 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆20Updated last year
- Time to Digital Converter on an FPGA☆13Updated 4 years ago
- ☆28Updated 4 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆26Updated 3 years ago
- Verilog implementation of a tapped delay line TDC☆36Updated 6 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆29Updated 4 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆43Updated 2 years ago
- ISP☆11Updated 11 months ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆19Updated 8 years ago
- This project aims to integrate image acquisition with AI acceleration to achieve functions such as multi-channel video source input captu…☆15Updated last year
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- 基于安路开发板的bayer视频简单处理☆16Updated 3 months ago
- 基于FPGA的三速以太网UDP协议栈设计☆18Updated 7 months ago
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆56Updated 9 years ago
- MIPI CSI-2 RX☆29Updated 3 years ago
- I2C Master and Slave☆29Updated 9 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆41Updated 2 years ago
- 这是使用FPGA开发CMOS的两个真实项目,之前的fpga_design仅是一个未完善的版本,同时也删除了一些与项目无关的东西☆32Updated 7 years ago
- 基于FPGA的FFT☆12Updated 5 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆24Updated 8 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆53Updated 2 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆14Updated 4 years ago
- This is use FPGA of Xilinx ZYNQ-7000 ZC702☆17Updated 7 years ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- Integration of SIFT and LES Algorithms☆11Updated 6 months ago
- Interface Protocol in Verilog☆47Updated 5 years ago