PranavGovekar / tdcOnFPGALinks
Implementation of tappped delay line TDC on FPGA
☆13Updated 3 years ago
Alternatives and similar repositories for tdcOnFPGA
Users that are interested in tdcOnFPGA are comparing it to the libraries listed below
Sorting:
- ☆12Updated 3 years ago
- Time to Digital Converter on an FPGA☆18Updated 5 years ago
- Verilog implementation of a tapped delay line TDC☆46Updated 7 years ago
- A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.☆23Updated 8 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆70Updated 4 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆62Updated 3 years ago
- kintex7 ov13850 fpga mipi camera☆20Updated 2 months ago
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆68Updated 11 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆32Updated 2 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 13 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Updated 5 years ago
- Fixed Point Kalman filter for fpga☆23Updated 5 years ago
- ☆19Updated 2 years ago
- ☆34Updated 6 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆25Updated 9 years ago
- AMC module with Xilinx RF-SoC and two analog front-end mezzanines for SDR and quantum applications☆42Updated 3 years ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆43Updated last month
- Python productivity for RFSoC platforms☆87Updated 3 months ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆22Updated 10 years ago
- FPGA based 30ps RMS TDCs☆91Updated 7 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆64Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆116Updated 2 years ago
- High-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆10Updated 5 years ago
- 基于FPGA的FFT☆19Updated 6 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆20Updated 6 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆15Updated 2 years ago
- Applying various image enhancement algorithms on Night Vision IR images using Xilinx Vivado☆14Updated 2 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆59Updated this week
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆76Updated 2 months ago