quartiq / redpid
migen + misoc + redpitaya = digital servo
☆37Updated 6 years ago
Alternatives and similar repositories for redpid:
Users that are interested in redpid are comparing it to the libraries listed below
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆57Updated 3 years ago
- SDK for FPGA / Linux Instruments☆99Updated 2 weeks ago
- AMC module with Xilinx RF-SoC and two analog front-end mezzanines for SDR and quantum applications☆39Updated 2 years ago
- Board repo for the ZCU216 RFSOC☆25Updated 2 years ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- FPGA Based lock in amplifier☆33Updated last year
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆60Updated 10 years ago
- Digital Phase-locked-loop software for Locking a Frequency Comb using a Red Pitaya☆39Updated 10 months ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 2 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆43Updated 3 years ago
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆42Updated 3 months ago
- NIST digital servo: an FPGA based fast digital feedback controller☆71Updated 7 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆55Updated this week
- Repository for the development of an FPGA based DSP Lock-In Amplifier☆63Updated last year
- Extensible FPGA control platform☆59Updated last year
- Collections of guides and projects related to testing RedPitaya☆52Updated 5 years ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 4 years ago
- Transform the Red Pitaya in an acquisition card☆29Updated 3 years ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆58Updated 4 years ago
- Small footprint and configurable JESD204B core☆41Updated 2 months ago
- Serial communication link bit error rate tester simulator, written in Python.☆105Updated this week
- A collection of phase locked loop (PLL) related projects☆103Updated last year
- ☆18Updated 2 years ago
- ☆30Updated 4 years ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆20Updated 9 years ago
- Verilog implementation of a tapped delay line TDC☆39Updated 6 years ago
- FPGA based 30ps RMS TDCs☆82Updated 7 years ago