Alternatives and similar repositories for redpid

Users that are interested in redpid are comparing it to the libraries listed below

• Koheron / koheron-sdk
  SDK for FPGA / Linux Instruments
  ☆102Updated this week
• m-labs / tdc-core
  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
  ☆61Updated 10 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆43Updated 3 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 4 years ago
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆63Updated 3 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆107Updated last year
• yrrapt / caravel_amsat_txrx_ic
  ☆30Updated 4 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆88Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆62Updated this week
• ipbus / ipbus-firmware
  Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol
  ☆42Updated 3 weeks ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆115Updated 4 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆69Updated 7 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated last month
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆46Updated last year
• capn-freako / PyBERT
  Serial communication link bit error rate tester simulator, written in Python.
  ☆110Updated this week
• mattvenn / fpga-sdft
  sliding DFT for FPGA, targetting Lattice ICE40 1k
  ☆77Updated 5 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆72Updated 3 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆82Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• nkrackow / SingularitySurfer-FPGA-Lock-In-Amplifier
  Repository for the development of an FPGA based DSP Lock-In Amplifier
  ☆67Updated 2 years ago
• frobino / axi_custom_ip_tb
  A testbench for an axi lite custom IP
  ☆23Updated 10 years ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• ZipCPU / dspfilters
  A collection of demonstration digital filters
  ☆154Updated last year
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆42Updated 5 years ago